3-Level DAC Bypass and Cell Power Gating for Delta-Sigma Noise

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Solution Overview

Problem

Delta Sigma converters face challenges in optimizing power consumption while maintaining high signal-to-noise ratio (SNR) and total harmonic distortion (THD) performance, particularly in battery-driven audio devices, where existing methods fail to efficiently manage power usage during small signal operations.

Innovation Solution

A bypass scheme and dynamic power management system are introduced, where a 3-level digital-to-analog converter (DAC) includes a bypass current path to shunt current sources, keeping the DAC powered on and reducing toggling activity for small signals, and a multiplexor system powers down DAC cells when not in use, using a charge amplifier to quickly power them back up when needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If DAC cells are powered down to reduce power consumption, then power efficiency improves, but signal quality and response time deteriorate

Engineering Contradiction:

Improvepower consumptionVSAvoidsignal quality

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent divides the DAC into multiple independently controllable DAC cells that can be selectively powered down. Each DAC cell can be independently controlled to be in either an active or powered-down state based on signal requirements, allowing granular power management while maintaining signal quality when needed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a look-ahead mechanism that anticipates signal level changes and pre-activates DAC cells before they are needed. This preliminary action ensures that when the signal exceeds the threshold, the DAC cells are already ready to contribute, avoiding signal quality degradation and reducing activation latency.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If all DAC cells remain powered on to maintain signal quality, then signal-to-noise ratio improves, but power consumption increases

Engineering Contradiction:

Improvesignal-to-noise ratioVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management where the power state of DAC cells changes based on real-time signal conditions. The system continuously monitors the input signal level and dynamically adjusts which DAC cells are active, transitioning between low-power and high-performance states to match actual signal requirements.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter (power state) of DAC cells based on signal amplitude thresholds. When the signal exceeds a predetermined threshold, additional DAC cells are activated to maintain signal-to-noise ratio; when the signal is below the threshold, fewer cells remain active to reduce power consumption.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If DAC cells are powered down for small signals, then power efficiency improves, but activation time increases

Engineering Contradiction:

Improvepower efficiencyVSAvoidactivation time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent uses a look-ahead mechanism that detects upcoming signal level increases before they occur and pre-activates the required DAC cells in advance. This preliminary activation eliminates the delay that would otherwise occur when cells need to be powered up on demand, maintaining fast response time while still achieving power savings during low-signal periods.

Inventive Principle:

Principle #10Preliminary action

4Productivity

If bypass path is used to shunt current sources, then toggling activity reduces, but circuit complexity increases

Engineering Contradiction:

Improvetoggling activityVSAvoidcircuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a bypass current path that acts as an intermediary for current sources during small signal operations. Instead of routing all current through the main DAC switching network, the bypass path provides an alternative route that reduces toggling activity in the main path while maintaining proper current flow, thereby reducing switching overhead without fundamentally altering the core DAC architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11509327B2System and method to enhance noise performance in a delta sigma converter

Publication Date: 2022.11.22 ANALOG DEVICES INC

AI summary

Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.