Analogue Conversion TRIZ Cases

Staggering delta-sigma ADC start timings cuts power and ground fluctuations, improving image sensor conversion accuracy and image quality.

A dual-filter A/D converter outputs fast lower-bit data before high-resolution data, cutting latency while preserving accurate sensor control.

A noise detection circuit uses common-electrode timing to switch between real-time and synced touch processing for accurate stylus coordinates.

A programmable drive-sense circuit configures single-line load sensing to cut power use, reject noise, and support concurrent sensing and actuation.

Phase-shifted extended Barker codes in microphone delta-sigma modulators suppress idle tone intermodulation while preserving a low noise floor.

Unique sensor frequencies plus FFT-based decoding enable dense touch arrays to cut serial sampling latency and readout complexity.

Segmented pull-up and pull-down drivers offset impedance non-linearity to keep PAM4 voltage margins consistent for reliable decoding.

A two-stage quantizer loop decouples ADC resolution from feedback DAC bits, cutting DAC area while improving stable amplitude.

A cascaded delta-sigma modulator separates quantization and clipping error shaping to keep SNDR high across a wider input range.

Passive low-pass feedback shapes quantization noise to achieve second-order sigma-delta performance with lower power and better loop stability.

A second passive loop converts and cancels quantization errors, cutting power use while improving SNR and metastability tolerance.

Low-noise detection and zero-cross power-down cut headphone ANC energy use while avoiding pop noise during mode changes.

Programmable delta-sigma gain stages keep phase fixed while tracking haptic transducer impedance and displacement to prevent over-excursion.

A DC detector enables the delta-sigma modulator only when DC is present, cutting transmit power use while suppressing in-band noise.

A passive sample-and-hold with timed switches feeds a decaying input to cut full-scale delta-sigma noise and improve AD conversion accuracy.

Windowed sinusoidal and transition waveforms cut radiated emissions while preserving SNR for touch, glove, and hover sensing.

A parallel-series PGA feedback resistor network cuts equivalent resistance to lower thermal noise, power use, die area, and gain error.

Polyphase interpolation and DDS parallelization cut sampling-rate demands while preserving SNR for contiguous and non-contiguous multiband RF transmission.

A bypass current path and selective DAC cell shutdown cut idle power in delta-sigma converters while preserving SNR, THD, and fast reactivation.

A level detector powers down ANC processing during low-noise periods and restores it when noise rises, cutting headphone power use.

A dual-code quantizer increases PWM edge separation at high levels to cut ISI and THDN without pop-click noise or higher idle noise.

A battery-following ADC reference expands hearing aid input range to avoid clipping and preserve speech clarity in loud environments.

Variable reference voltages let a capacitive pressure sensor measure and correct mechanical and thermal stress drift for stable lifetime accuracy.

A feedback-loop amplifier in a delta-sigma modulator boosts SNR by amplifying the error signal while avoiding saturation and clipping.

Controlled-delay quad switching in a multibit DAC cuts mismatch-driven distortion and meets excess loop delay limits in sigma-delta modulators.

Parallel sensor signals are combined with adaptive weighting and loop filtering to cut latency and improve signal-to-noise in angular position tracking.

A cascaded VCO-based ADC cancels quantizer nonlinearity with residue correction to improve SNR, bandwidth, and low-power operation.

A VCO-based Delta-Sigma error ADC shifts Class-D amplifier feedback into the digital domain, reducing analog precision demands and circuit complexity.

Two ADCs split MSB and LSB quantization across one sampling period to extend bit decision time and cut CTDSM quantization noise.

A feedforward capacitor and compensating zero restore DAC settling and feedback stability in high-speed continuous-time sigma-delta ADCs.

Switching or reversing sensing and reference capacitor connections on saturation extends CDC measurement range without larger reference capacitors.

Unused DAC current during the return-to-zero interval corrects input offset, improving sensor signal quality with less power and chip area.

Low-voltage, low-frequency digital microbeamforming cuts probe heat and cable bulk while supporting compact 2D and 3D ultrasound imaging.

Cascaded dynamic preamplifier stages suppress comparator offset while preserving ADC conversion speed and PVT robustness for Lidar.

Measured vibration tunes ADC gain and window width to cut noise and phase delay in VCM head-position control.

On-chip ADC calibration computes DAC bit weights, offset, and gain to remove external trimming while improving accuracy and repeatability.

A single-node channel driver uses differential sensing and sigma-delta noise shaping to improve touch accuracy with fewer integration cycles.

By combining resistive-input sigma-delta and switched-capacitor ADC paths, this case achieves alias-free bandwidth with strong DC precision.

Computes ADC output samples only when needed and powers off the sigma-delta modulator during unused intervals to cut idle power.

Delta-sigma digitization separates quantization noise from low-frequency signals, enabling longer HFC optical links and higher modulation orders.

A sigma-delta-controlled delay chain spreads clock energy to manage EMI while cutting delay elements, power use, and hardware cost.

Selective common-mode biasing lets a Class-D amplifier switch output modes while minimizing DC transducer current without sacrificing dynamic range or SNR.

Sequential charge sharing and residue accumulation help noise-shaping SAR ADCs transfer ~1 mV residues with higher conversion accuracy.

A diagnostic circuit checks ADC input thresholds so the controller can detect false saturation and block faulty clipped sensor data.

A range control circuit adjusts the subtrahend from the bitstream, enabling single-bit delta-sigma conversion across high dynamic range with low power.

Presetting the loop filter output during reset limits difference-signal swings and reduces non-linear errors in incremental delta-sigma ADCs.

A synchronized low-duty LED drive clock cuts photocoupler power use and LED stress while maintaining reliable insulated communication.

A resistive-input sigma-delta stage paired with a switched-capacitor ADC solves the bandwidth, aliasing, and DC precision tradeoff.

Oversampling and noise shaping digitize multi-RAT fronthaul signals with two or fewer bits, improving spectral efficiency and simplifying RRHs.

Correlating quantization noise across differential sigma-delta outputs cuts folded-back power dissipation when driving low-impedance loads.