Pipelined Dynamic Preamplifier for Fast Low-Offset ADC Comparison
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Solution Overview
Problem
High-speed automotive Lidar systems require high-speed analog-to-digital converters with moderate resolution, but existing technologies face challenges in minimizing comparator offset while maintaining speed and robustness over PVT variations, and achieving sufficient gain in preamplifiers to suppress offset in high-speed applications.
Innovation Solution
A pipelined dynamic preamplifier system with cascaded gains and sample-and-hold stages, including a regenerative latch and sampling switches, which allows for self-calibration during operation to minimize comparator offset and achieve high gain without sacrificing conversion speed, and is tolerant to PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional preamplifier structure is used to achieve high gain, then the comparator offset is suppressed, but the conversion speed is reduced and the circuit becomes complex
Solution Approach 1:
The preamplifier is divided into multiple stages (first preamplifier, second preamplifier, third preamplifier) with different gain levels. The first stage provides high gain for offset suppression, while subsequent stages provide additional gain without proportionally increasing complexity or reducing speed, as each stage operates independently with optimized transistor sizing.
Solution Approach 2:
Different transistor sizes are used in different stages of the preamplifier. The first preamplifier uses larger transistors to achieve high gain and suppress offset, while later stages use smaller transistors to maintain speed and reduce complexity. This local optimization allows each stage to perform its specific function efficiently.
2Measurement precision
If transistor size is increased to reduce comparator offset, then offset suppression improves, but conversion speed decreases due to increased parasitic capacitors
Solution Approach 1:
The gain requirement is segmented across multiple preamplifier stages rather than requiring a single large transistor. The first stage uses larger transistors for offset suppression, while subsequent stages use smaller transistors for additional gain, collectively achieving the required total gain without requiring any single transistor to be excessively large.
Solution Approach 2:
Transistor sizes are locally optimized for each stage's specific function. The first preamplifier stage uses larger transistors where high gain is critical for offset suppression, while later stages use smaller transistors where speed is more critical, achieving overall system optimization rather than uniform sizing.
3Speed
If a pipelined dynamic preamplifier with cascaded gains is used, then conversion speed is maintained, but the circuit complexity increases
Solution Approach 1:
Multiple preamplifier stages are merged into a single pipelined dynamic preamplifier structure with shared control signals and clocking. The stages operate in a coordinated manner with common sampling switches and regenerative latches, reducing the overall control complexity compared to independent stages while maintaining the speed benefits of cascaded gains.
Solution Approach 2:
The pipelined dynamic preamplifier uses periodic clocking and sampling phases to coordinate the operation of multiple stages. Each stage processes signals in alternating phases, allowing the circuit to maintain high conversion speed while using simple periodic control signals rather than complex independent control logic for each stage.
4Measurement precision
If high gain is achieved in preamplifier to suppress offset, then measurement precision improves, but the circuit becomes more sensitive to PVT variations
Solution Approach 1:
The high gain requirement is segmented across multiple preamplifier stages rather than achieved in a single stage. This segmentation reduces the gain burden on any single stage, making each stage less sensitive to PVT variations while collectively achieving the required total gain for effective offset suppression.
Solution Approach 2:
Each preamplifier stage is locally optimized with appropriate transistor sizing to achieve the required gain while maintaining robustness. The first stage uses larger transistors for high gain and offset suppression, while subsequent stages use smaller transistors that are more robust to PVT variations, achieving a balance between precision and reliability.
Data Source
AI summary
A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.