Interleaved CT Delta-Sigma Quantizer for Longer Bit Decision Time
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Solution Overview
Problem
Continuous-time delta-sigma modulators face instability and increased quantization noise due to excess loop delay, which restricts bit decision time and wastes sampling period, especially with wider bandwidths and faster sampling rates.
Innovation Solution
The implementation of a CTDSM with two distinct ADCs that sample different parts of the output signal at different times within the sampling period, utilizing a first ADC for most significant bits (MSBs) and a second ADC for least significant bits (LSBs), with carefully managed clock signals and delay circuits to fully utilize the sampling period and reduce quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the excess loop delay is reduced to maintain stability, then the CTDSM loop stability is improved, but the bit decision time is restricted and sampling period is wasted
Solution Approach 1:
The quantization process is divided into two separate steps: a first quantizer processes the signal at time T1 to produce MSBs, and a second quantizer processes the same signal at time T2 to produce LSBs. This segmentation allows the system to utilize the entire sampling period by performing quantization operations at different time instances, thereby resolving the contradiction between maintaining loop stability (requiring small ELD) and充分利用 the sampling period for bit decisions.
2Speed
If the sampling rate is increased to achieve wider bandwidth, then the CTDSM bandwidth is improved, but the bit decision time becomes insufficient
Solution Approach 1:
The system maintains continuous useful action by overlapping the operation of two quantizers within one sampling period. While the first quantizer operates during the first half of the sampling period, the second quantizer operates during the second half, ensuring that the quantization function continues without interruption throughout the sampling period. This allows the CTDSM to achieve wider bandwidth with faster sampling rates while maintaining sufficient bit decision time through the continuous utilization of the sampling period.
Data Source
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AI summary
The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.