Incremental Delta-Sigma ADC Preset Circuit for Reset Accuracy
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Solution Overview
Problem
The reset procedure in incremental delta-sigma analog-to-digital converters (ADCs) induces non-linear errors due to the dramatic variation of the difference signal at the beginning of each conversion cycle, affecting the accuracy of the conversion process.
Innovation Solution
Incorporating a preset circuit within the loop filter that presets the output terminal during the reset phase, ensuring that the analog integrators and digital components operate within their linear regions by maintaining a non-zero value, thereby reducing non-linear errors and improving the accuracy of the incremental ADC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the analog integrators are reset after each conversion cycle, then the incremental ADC can perform continuous conversions, but non-linear errors are introduced due to dramatic signal variation
Solution Approach 1:
The patent applies preliminary action by presetting the loop filter output to a specific value (e.g., half of the full-scale range) before the reset phase begins. This preliminary presetting prevents the dramatic signal variation that would otherwise occur when the integrators are reset, thereby eliminating non-linear errors while maintaining continuous conversion capability. The preset value is maintained throughout the reset phase to ensure the analog integrators operate within their linear region.
2Measurement precision
If the loop filter output is preset during reset phase, then non-linear errors are reduced, but additional circuit components are required
Solution Approach 1:
The patent implements multi-functionality by designing the preset circuit to serve multiple purposes: it presets the loop filter output during the reset phase to prevent non-linear errors, and the same circuit structure can be integrated into the existing delta-sigma modulator architecture. The preset circuit uses standard components (switches, resistors, capacitors) that are already present in the ADC, making the solution space-efficient and not significantly increasing overall device complexity.
Data Source
AI summary
An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.