Continuous-Time Sigma-Delta ADC Loop Delay Recovery Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Sigma-delta analog-to-digital converters (ADCs) face performance degradation due to excess loop delay (ELD) caused by parasitic capacitance, leading to incomplete settling of feedback information and potential instability, especially in high-speed applications.
Innovation Solution
Incorporating feedforward capacitors in parallel with the current digital-to-analog converter (DAC) and transconductance cells with compensating zeros in the transfer function to mitigate parasitic capacitance effects, thereby improving settling speed and stability of the feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ELD DAC is used to reduce excess loop delay impact, then ADC performance is improved, but parasitic capacitance causes incomplete settling and potential instability
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by introducing a separate compensation capacitor connected to the DAC output node. This compensation capacitor is specifically designed to counteract the parasitic capacitance, allowing the main feedback loop to operate without the detrimental effects of the parasitic elements on the summing node.
Solution Approach 2:
The compensation capacitor acts as an intermediary element between the DAC output and the summing node. It mediates the interaction between the DAC signal and the parasitic capacitance, enabling the system to achieve proper settling by providing an additional charge storage mechanism that compensates for the parasitic effects.
2Productivity
If feedback loop speed is increased for high-speed ADC applications, then conversion speed is improved, but excess loop delay causes performance degradation
Solution Approach 1:
The compensation capacitor is configured to act in advance of the main feedback loop settling process. By providing preliminary charge storage and release mechanisms through the compensation capacitor, the system prepares the voltage at the summing node to settle more quickly, effectively anticipating and preventing the settling issues that would otherwise occur at high speeds.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.