Spread Spectrum Clock Circuit With Fewer Delay Elements for EMI Control
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Solution Overview
Problem
As System on Chip (SoC) digital circuit designs increase clock signal frequency, they face significant electromagnetic interference (EMI) issues, which existing spread spectrum clock generation circuits attempt to mitigate but often require an excessive number of delay elements in the delay chain circuit, leading to inefficiencies.
Innovation Solution
A spread spectrum clock generator circuit utilizing a delay chain with a multiplexer and a control circuit that includes a sigma-delta modulator to generate a modulated digital signal for selecting phase-shifted clock signals, reducing the number of delay elements needed by leveraging noise shaping and low-pass filtering to achieve similar error tolerance with fewer components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is increased to improve processing speed, then the operating frequency is improved, but electromagnetic interference increases
Solution Approach 1:
The patent applies dynamics by continuously varying the phase of the clock signal over time through a delay chain and multiplexer controlled by a dither signal. Instead of using a fixed high-frequency clock, the system dynamically adjusts the clock phase to spread spectral energy, reducing peak electromagnetic interference while maintaining the high operating frequency needed for processing speed.
Solution Approach 2:
The patent changes the temporal parameter of the clock signal by introducing phase modulation through a dither signal. The control signal varies the delay through the delay chain, causing the output clock phase to fluctuate over time. This parameter change spreads the clock signal's spectral content across a wider frequency range, reducing EMI while preserving the fundamental operating frequency.
2Object-generated harmful factors
If traditional spread spectrum clock generation is used to reduce EMI, then electromagnetic interference is reduced, but the number of delay elements increases excessively
Solution Approach 1:
The patent uses partial action by applying a small-amplitude dither signal to the control input of the multiplexer rather than requiring extensive delay elements. Instead of creating many phase-shifted versions of the clock signal, the system uses a limited number of delay elements with a dynamically varying control signal that provides the necessary phase modulation for spread spectrum operation, reducing hardware complexity.
Solution Approach 2:
The patent replaces the mechanical approach of using many physical delay elements with a control signal-based approach. Instead of increasing the physical size of the delay chain hardware, the system uses a digitally generated dither signal to achieve phase modulation, substituting hardware complexity with software/control signal complexity.
Data Source
AI summary
A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.