Self-Calibrating Non-Binary DAC With On-Chip ADC Correction

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Solution Overview

Problem

High-accuracy digital-to-analog converters (DACs) require costly analog trimming procedures and external hardware for error correction, limiting their implementation and repeatability in precision applications.

Innovation Solution

A self-calibrating DAC system that uses an on-chip delta-sigma ADC to calculate bit weightages, offset, and gain coefficients, eliminating the need for external components and trimming by performing digital calibration within the DAC, allowing for high-accuracy measurements and reduced hardware overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If external components and post-manufacture trimming are used for error correction, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
ImproveDAC output voltage accuracyVSAvoidexternal components and trimming circuitry
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the error correction functionality into the DAC chip itself by integrating an ADC, calibration logic, and lookup table onto the same chip. This merging eliminates the need for external calibration components and post-manufacture trimming circuits, thereby reducing device complexity while maintaining manufacturing precision through on-chip digital calibration.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The DAC performs self-calibration by using its own integrated ADC to measure its output and automatically adjust its operation through digital correction codes stored in the lookup table. This self-service approach eliminates the need for external trimming equipment and manual calibration procedures, reducing both device complexity and calibration overhead.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If external components are used for error correction, then manufacturing precision is improved, but ease of manufacture deteriorates

Engineering Contradiction:
ImproveDAC output voltage accuracyVSAvoidintegration and assembly process
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

By merging the ADC, calibration logic, and lookup table onto the same chip as the DAC, the patent eliminates the need for assembling multiple external components. This integration simplifies the manufacturing process, reduces assembly steps, and improves ease of manufacture while maintaining high manufacturing precision through on-chip digital calibration.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If digital calibration is implemented, then device complexity is reduced, but measurement precision requirements increase

Engineering Contradiction:
Improvecalibration hardwareVSAvoidADC measurement accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent makes the ADC serve multiple functions: it acts as both the measurement device for calibration and as part of the DAC system during normal operation. This multi-functionality allows the use of a single ADC component to meet both measurement precision requirements and system functionality, reducing the need for separate high-precision measurement devices while maintaining calibration accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11356111B1Self calibrating digital-to-analog converter
Publication Date: 2022.06.07 NXP BV
  • US11356111B1 patent drawing
  • US11356111B1 patent drawing
  • US11356111B1 patent drawing

AI summary

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes an input port, a non-binary DAC, an ADC to receive an output of the non-binary DAC, a lookup table to store a plurality of calibration code and a calibration logic coupled with the non-binary DAC. The self-calibrating DAC has two modes of operations, a calibration mode and a normal operational mode. In the calibration mode, the self-calibrating DAC is configured to calculate weightages of the non-binary DAC and to calculate an offset coefficient and a gain coefficients using high precision on chip analog-to-digital converter (ADC).