Delta-Sigma DAC Offset Compensation Using Return-to-Zero Current

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Solution Overview

Problem

Integrated sensor applications face challenges in maximizing the signal/noise ratio due to strong offset signals, which often require additional calibration circuits, increasing power consumption and semiconductor area occupation.

Innovation Solution

A circuit that performs offset compensation within the digital-to-analog converter (DAC) in a delta-sigma converter, avoiding the need for additional circuitry and current consumption, by utilizing unused current in the DAC for offset correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If additional calibration circuits are added to compensate for offset signals, then offset compensation performance is improved, but power consumption and semiconductor area occupation increase

Engineering Contradiction:
Improveoffset compensation performanceVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent merges the offset compensation function with the existing DAC circuit by utilizing the return-to-zero interval to redirect current through the offset compensation path instead of disabling it. This integration eliminates the need for separate calibration circuits while maintaining offset compensation performance, thereby reducing power consumption and semiconductor area occupation.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If additional calibration circuits are added to compensate for offset signals, then offset compensation performance is improved, but semiconductor area occupation increases

Engineering Contradiction:
Improveoffset compensation performanceVSAvoidsemiconductor area occupation
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent combines the offset compensation functionality into the existing DAC structure by using the return-to-zero interval to switch current paths. This merging approach eliminates the need for additional calibration circuits, thereby reducing semiconductor area occupation while maintaining effective offset compensation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The DAC circuit is designed to perform multiple functions: normal digital-to-analog conversion during the active interval and offset compensation during the return-to-zero interval. This multi-functionality allows the same circuit hardware to serve dual purposes, reducing the need for dedicated offset compensation circuits and thereby reducing semiconductor area occupation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If the DAC is disabled during return-to-zero interval to reduce power consumption, then power consumption is reduced, but offset compensation capability is lost

Engineering Contradiction:
Improvepower consumptionVSAvoidoffset compensation capability
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent employs periodic switching of the DAC current path, utilizing the return-to-zero interval periodically to perform offset compensation. During normal operation intervals, the DAC functions as usual, and during return-to-zero intervals, the current is redirected through the offset compensation path. This periodic action enables both power savings and continuous offset compensation capability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system uses its own return-to-zero interval, which would otherwise be a period of idle current flow, to perform offset compensation. By self-utilizing this interval for compensation purposes, the system achieves offset compensation capability without requiring external calibration circuits or additional power consumption during active intervals.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11368165B2Converter circuit, corresponding device and offset compensation method
Publication Date: 2022.06.21 STMICROELECTRONICS SRL
  • US11368165B2 patent drawing
  • US11368165B2 patent drawing
  • US11368165B2 patent drawing

AI summary

A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.