Sample-and-Hold Delta-Sigma Circuit for Full-Scale Noise Reduction
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Solution Overview
Problem
Incremental delta-sigma modulators suffer from increased noise and variance in digital output signals when input signals approach the full-scale value, limiting the usable range of the input signal and affecting accuracy in signal and reference signal conversions.
Innovation Solution
A circuitry incorporating a passive sample-and-hold element with a capacitor and switches is used, where the capacitor is charged during the reset phase of the delta-sigma modulator and connected during conversion, providing a decaying input voltage to the incremental delta-sigma modulator, and a lossy integrator is employed in the decimation filter to adapt weighting of output bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delta-sigma modulator is used for AD conversion, then high resolution and noise shaping are achieved, but increased noise and variance occur when input signals approach the full-scale value
Solution Approach 1:
The input signal is preprocessed by a sample-and-hold circuit before entering the delta-sigma modulator. This preliminary action maintains a constant input voltage during conversion, preventing the signal from approaching full-scale values that cause noise and variance, thereby resolving the contradiction between maintaining measurement precision and avoiding harmful noise effects
Solution Approach 2:
A sample-and-hold circuit is introduced as an intermediary element between the input signal and the delta-sigma modulator. This mediator captures the input voltage and holds it constant, preventing direct interaction between the varying input signal and the modulator's full-scale threshold, thus reducing noise and variance while preserving conversion accuracy
2Adaptability or versatility
If the input signal range is extended to include signals near full-scale, then the usable range increases, but noise and variance increase significantly
Solution Approach 1:
The sample-and-hold circuit performs preliminary action by capturing and stabilizing the input voltage before it enters the modulator. This allows the system to accept a wider range of input signals including those near full-scale, while the held constant voltage prevents the noise and variance that would otherwise occur, thus extending usable range without sacrificing reliability
Solution Approach 2:
The sample-and-hold circuit acts as an intermediary that decouples the input signal range from the modulator's noise-sensitive operation. It allows wide adaptability by accepting various input levels while maintaining reliable output by presenting a stable, held voltage to the modulator, preventing noise amplification
3Stability of the object's composition
If a sample-and-hold element with active amplifier is used, then input voltage stability is maintained, but device complexity and power consumption increase
Solution Approach 1:
The active amplifier component is extracted and removed from the sample-and-hold circuit. Instead of using an active amplifier to maintain input voltage stability, the patent uses a passive implementation with switches and capacitors, reducing device complexity and power consumption while still achieving the required voltage stability during conversion
Solution Approach 2:
The sample-and-hold circuit is designed to be self-sufficient without requiring an active amplifier. The held voltage is maintained through the natural properties of capacitors and switch timing, allowing the circuit to serve itself and eliminate the need for additional active components, thus reducing complexity while maintaining stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces noise and variance, allowing a larger range of the input signal to be used effectively and improving the accuracy of AD conversions, especially near maximum input signals, by ensuring quasi-random behavior of the output bitstream and optimizing the decimation filter's weighting.
Implementation Method 1
the sample-and-hold element includes a capacitor for charging the input voltage for the incremental delta-sigma modulator
Data Source
AI summary
A circuitry for an incremental delta-sigma modulator includes at least an incremental delta-sigma modulator and a sample-and-hold element, the sample-and-hold element being arranged in front of the incremental delta-sigma modulator and providing an input voltage for the incremental delta-sigma modulator in the charged state, wherein the sample-and-hold element includes a capacitor for charging the input voltage for the incremental delta-sigma modulator, wherein a first switch is arranged in front of the capacitor, and a second switch is arranged behind the capacitor, wherein the first switch is open when the second switch is closed so as to provide, at the incremental delta-sigma modulator, an input voltage decreasing in amount, in particular a decaying input voltage, or wherein the second switch is open when the first switch is closed so as to charge the capacitor of the sample-and-hold element. In addition, a method of operating a circuitry for an incremental delta-sigma modulator is proposed.