DDR Quad-Switched Multibit DAC for Low-Distortion Sigma-Delta Loops
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-bit sigma-delta modulator circuits face non-linearity issues due to mismatch in unit resistive DAC elements, leading to increased noise floor and harmonic distortion, which complicates meeting the excess loop delay requirements, especially at high sampling frequencies.
Innovation Solution
Implementing a double data rate (DDR) quad switching scheme for the DAC circuit, where quad switching signals are generated with controlled delays to ensure excess loop delay constraints are met and minimize glitches, thereby reducing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-bit quantization is used in sigma-delta modulator circuits, then resolution and sampling rate performance is improved, but DAC element mismatch causes non-linearity that increases noise floor and harmonic distortion
Solution Approach 1:
The patent implements dynamic element matching (DEM) that randomly switches between different DAC elements on a sample-by-sample basis. This dynamic switching mechanism ensures that each DAC element is used equally over time, eliminating the non-linearity caused by static element mismatch while maintaining multi-bit quantization benefits for resolution and sampling rate performance.
Solution Approach 2:
The patent employs feedback mechanisms where the quantization noise is shaped to higher frequencies through noise shaping filters. This feedback approach pushes the harmful quantization noise away from the signal band, allowing the multi-bit DAC to operate with reduced in-band distortion while maintaining high resolution through the feedback loop's noise suppression.
2Device complexity
If conventional switching schemes are used in multi-bit DAC circuits, then circuit complexity is reduced, but excess loop delay increases which complicates meeting timing requirements at high sampling frequencies
Solution Approach 1:
The patent segments the switching operation into multiple phases within each clock cycle, using separate switch groups for different timing slots. This segmentation allows parallel processing of multiple data bits without increasing overall circuit complexity, as each switch group operates independently with simplified control logic, thereby reducing excess loop delay while maintaining manageable device complexity.
Solution Approach 2:
The patent implements periodic switching sequences where DAC elements are activated in a predetermined periodic pattern throughout the sampling period. This periodic action optimizes the timing distribution of switching operations, ensuring that critical switching events are spaced to minimize peak delay requirements while maintaining simple periodic control logic that does not increase device complexity.
3Speed
If quad switching signals are generated without controlled delays, then circuit operation speed is improved, but residual distortion increases due to uncontrolled excess loop delay
Solution Approach 1:
The patent applies preliminary delay adjustments to the quad switching signals before they reach the DAC elements. By pre-calculating and applying the required delay compensation in advance, the system maintains high switching speed while ensuring that the total excess loop delay remains within acceptable limits, thereby preventing residual distortion without sacrificing operating speed.
Solution Approach 2:
The patent dynamically adjusts the delay parameters of the quad switching signals based on the specific operating conditions and data patterns. By changing the delay parameters adaptively, the system optimizes the balance between switching speed and distortion control, maintaining high speed operation while keeping residual distortion minimal through parameter optimization rather than fixed conservative delay settings.
Data Source
AI summary
A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.