High-Resolution DAC Calibration for Major Transition Glitch Control
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Solution Overview
Problem
Current digital to analog converters (DACs) with high resolution and monotonicity requirements, such as those needed for nanopositioning and servo control applications, face issues with glitch effects and undesired DC errors due to pulse width modulation during major bit transitions, which existing methods like sigma-delta modulation and dual DAC configurations cannot fully mitigate.
Innovation Solution
A digital analog conversion circuit that employs a calibration table to generate series of control values for DACs during major bit transitions, using non-linear interpolation and compensatory control values to address glitches and DC errors, particularly suited for high-resolution and monotonicity applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pulse width modulation is used to increase DAC resolution beyond 16 bit, then resolution is improved, but glitch effects and DC errors are generated during major bit transitions
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing corrected control values in a calibration table before actual DAC operation. The calibration table contains pre-computed compensation values that account for glitch effects and DC errors during major bit transitions. When a major bit transition is detected, the system retrieves the pre-prepared corrected control values from the calibration table, eliminating the need for real-time correction calculations and ensuring glitch-free operation.
Solution Approach 2:
The patent changes the parameter values in the calibration table based on the specific characteristics of the DAC and its transition behavior. The calibration process involves measuring actual glitch effects and DC errors during major bit transitions, then adjusting the control values in the calibration table to compensate for these effects. This parameter adjustment ensures that the corrected control values produce the desired output voltage without glitches or DC errors.
2Object-generated harmful factors
If two sigma-delta modulated DACs are used to overcome glitch effects, then glitch reduction is improved, but device complexity and DC offset remain issues
Solution Approach 1:
The patent extracts the glitch correction function from the dual DAC configuration and implements it through a single DAC with a calibration table. Instead of using two DACs to cancel out glitch effects, the solution extracts the essential correction information and stores it in a calibration table accessible by a single DAC. This extraction approach maintains glitch reduction effectiveness while eliminating the complexity of dual DAC architecture.
Solution Approach 2:
The patent creates a copy of the correction information in the form of a calibration table that stores pre-computed control values. Rather than physically duplicating the DAC hardware, the solution copies the corrective action data into a lookup table that can be quickly accessed during operation. This copying approach provides the benefits of glitch cancellation without the hardware duplication overhead.
3Measurement precision
If update frequency is increased to achieve higher resolution through pulse width modulation, then resolution is improved, but speed and productivity are reduced
Solution Approach 1:
The patent applies preliminary action by pre-calculating corrected control values during a calibration phase and storing them in the calibration table. During normal operation, the system simply retrieves these pre-computed values based on the input code, avoiding the need for complex real-time calculations. This approach maintains high update frequencies while achieving high effective resolution through the pre-prepared correction data.
Data Source
Figure 1~3
AI summary
To increase the accuracy and resolution of an m bit digital analog converter (2), n bit input values with n > m are fed to a control circuit (1) and converted to a series of control values for the digital analog converter (2) using dithering techniques. When the series of control values straddles a major transition where a large number of bits are switched between 1 and 0, a corrected series of control values is retrieved from a calibration table. The corrected series takes into account the glitch effects observed at the output of digital analog converter (2) at a major transition.