DAC High-Pass Compensation for Sinc Frequency Roll-Off
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Solution Overview
Problem
Digital to analog converters (DACs) exhibit a low-pass frequency response that attenuates higher frequency signal components, leading to undesired performance impacts in applications like broadband wireless communication, with existing compensation techniques facing limitations such as increased power consumption and complexity.
Innovation Solution
An n-bit digital to analog converter is designed with a high pass filter architecture that includes a receiving circuit, delay circuits, and current generation circuits to generate and combine bit signal streams with delayed and scaled currents, effectively providing a first-order high pass filter response to compensate for sinc attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DAC's input updating rate is increased to compensate for high frequency roll off, then the frequency response at high frequencies is improved, but the power consumption increases
Solution Approach 1:
The patent segments the compensation function into multiple parallel paths: a main DAC path and a parallel compensation path. The compensation path processes a delayed and inverted version of the input signal through separate current generation circuits, allowing frequency response correction without increasing the main DAC's updating rate, thus avoiding increased power consumption.
Solution Approach 2:
The patent introduces an intermediary compensation signal that is delayed by a delay circuit and inverted by an inverter before being combined with the main DAC output. This intermediary path provides the necessary high-frequency boost without requiring the main DAC to operate at higher updating rates, thereby maintaining low power consumption.
2Measurement precision
If a digital or analog high pass filter is added to compensate for sinc attenuation, then the frequency response is improved, but the device complexity increases
Solution Approach 1:
The patent merges the high pass filter functionality directly into the existing DAC current generation circuits. Instead of adding separate digital or analog filter stages, the compensation is achieved by combining outputs from existing current generation circuits that process delayed and inverted bit streams, thereby providing frequency response correction without increasing overall device complexity.
Solution Approach 2:
The patent makes the existing DAC components multi-functional by having current generation circuits process both the original input signal and the delayed/inverted compensation signal. This allows the same hardware blocks to perform both normal conversion and frequency response compensation, eliminating the need for additional dedicated filter circuits.
3Measurement precision
If the DAC's input updating rate is increased to compensate for high frequency roll off, then the frequency response at high frequencies is improved, but the conversion speed requirement increases
Solution Approach 1:
The patent segments the signal processing into parallel paths with different timing requirements. The compensation path operates on a delayed version of the input signal, allowing it to use a lower updating rate while still effectively compensating for high-frequency roll-off in the combined output, thus avoiding the need to increase the main DAC's conversion speed.
Solution Approach 2:
The patent introduces a delayed and inverted intermediate signal that serves as a compensation mechanism. This intermediary approach allows frequency response correction to be achieved at a lower updating rate in the compensation path, avoiding the need to increase the main DAC's conversion speed while still improving overall frequency response accuracy.
Data Source
AI summary
A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.