Damascene Via-Trench Patterning With Etch Stop Layer Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in forming via and trench openings during the damascene etching process, where the existing methods face issues with process complexity and undesired removal of dielectric layers.

Innovation Solution

A method involving the use of a photomask with a translucent layer and an opaque layer, where the translucent layer includes a mask opening of via feature and the opaque layer includes a mask opening of trench feature, allowing for a single step damascene etching process to form via and trench openings, and optionally employing an etch stop layer to prevent undesired removal of the first dielectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single step damascene etching process is used to form via and trench openings, then process complexity is reduced and productivity is improved, but undesired removal of the first dielectric layer occurs

Engineering Contradiction:
Improvesingle step etching processVSAvoidundesired removal of dielectric layer
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

An etch stop layer is introduced between the first dielectric layer and the second dielectric layer to act as a mediator that prevents undesired etching of the first dielectric layer during the single step damascene etching process, while still allowing the etch to proceed through the second dielectric layer to form the trench opening

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric stack is segmented into multiple layers with different etch stop layers positioned at specific locations to control the etching process selectively, allowing different regions to be etched to different depths in a single step process

Inventive Principle:
Principle #1Segmentation

2Reliability

If the etch stop layer is positioned between the first and second dielectric layers, then the first dielectric layer is protected from removal, but the etch stop layer adds an additional layer to the structure

Engineering Contradiction:
Improveprevention of dielectric layer removalVSAvoidadditional etch stop layer
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The etch stop layer is designed to automatically stop the etching process when reached, providing self-regulating protection to the first dielectric layer without requiring additional control mechanisms or process steps

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12142518B2Method for fabricating semiconductor device with damascene structure by using etch stop layer
Publication Date: 2024.11.12 NAN YA TECH
  • US12142518B2 patent drawing
  • US12142518B2 patent drawing
  • US12142518B2 patent drawing

AI summary

The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.