Data Alignment Circuit Switching Between PAM4 and NRZ Modes
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Solution Overview
Problem
Current electronic devices face challenges in efficiently aligning data at varying operating speeds, particularly in high-speed and low-speed operations, due to limitations in data formats such as return-to-zero and four-level pulse amplitude modulation formats.
Innovation Solution
An electronic device is designed with a comparison circuit, sampling circuit, and alignment circuit that can switch between two operation modes: one for high-speed operations using four-level pulse amplitude modulation and another for low-speed operations using non-return-to-zero format, allowing for reliable data alignment by adjusting pulse amplitude and maintaining logic levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If four-level pulse amplitude modulation format is used for high-speed operation, then operating speed is improved, but data alignment reliability deteriorates
Solution Approach 1:
The electronic device dynamically switches between first and second operation modes based on operating conditions. In the first mode (high-speed), four-level PAM format is used with three comparators for 2-bit data identification. In the second mode (low-speed), NRZ format is used with single-level data identification. This dynamic adaptation resolves the contradiction by selecting the appropriate operation mode to maintain reliability at different speed levels.
Solution Approach 2:
The system changes operational parameters including data format (PAM4 vs NRZ), number of comparators (three vs one), and sampling clock frequency based on the selected operation mode. These parameter changes enable the system to optimize between speed and reliability by adjusting the data identification approach according to operating requirements.
2Ease of operation
If return-to-zero format is used, then data identification is simplified, but operating speed is reduced
Solution Approach 1:
The system dynamically selects between RZ and NRZ formats based on operating mode. In first operation mode, RZ format provides simplified data identification with clear return-to-zero transitions. In second operation mode, NRZ format enables higher operating speeds by maintaining logic levels throughout the bit period. This dynamic selection resolves the speed-simplicity contradiction.
3Speed
If non-return-to-zero format is used, then operating speed is improved, but data alignment precision deteriorates
Solution Approach 1:
The system dynamically adjusts the data alignment approach based on operation mode. In second mode (NRZ format), data alignment is performed by maintaining logic levels throughout the bit period, which improves speed. The system compensates for potential precision issues by using appropriate sampling timing and clock synchronization mechanisms specific to NRZ format.
Solution Approach 2:
The system changes sampling clock frequency and data sampling timing parameters according to the selected operation mode. In NRZ mode, the sampling parameters are adjusted to match the maintained logic level characteristics, ensuring both speed improvement and adequate alignment precision.
4Adaptability or versatility
If three comparators are used for four-level PAM, then 2-bit data identification capability is improved, but device complexity increases
Solution Approach 1:
The system dynamically configures the number of comparators based on operation mode. In first mode, three comparators are activated to provide 2-bit data identification capability for high-speed PAM4 operation. In second mode, only one comparator is needed for simple NRZ data identification. This dynamic configuration reduces average device complexity while maintaining high adaptability when needed.
Data Source
AI summary
An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.