Data Bus Inversion Circuit With Selective Modes for Noise Reduction

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Solution Overview

Problem

Semiconductor apparatuses face issues such as simultaneous switching noise, crosstalk, and increased reference potential noise and current consumption when transmitting large amounts of data at high speeds, which existing data bus inversion (DBI) methods do not adequately address.

Innovation Solution

A data bus inversion circuit that selectively operates in two modes based on product information, either storing data without sorting it across multiple signal lines or sorting it, to generate a data bus inversion flag by comparing data, thereby reducing noise and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transmitted at high speed through many signal lines, then data processing speed is improved, but simultaneous switching noise, crosstalk, and current consumption increase

Engineering Contradiction:
Improvedata processing speedVSAvoidsimultaneous switching noise and crosstalk
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent applies data bus inversion by inverting the logic levels of data signals (0 becomes 1, 1 becomes 0) when the number of high logic value data exceeds half of the total data bits. This inversion reduces the number of simultaneous switching transitions, thereby decreasing simultaneous switching noise and crosstalk while maintaining high-speed data transmission capability

Inventive Principle:
Principle #13The other way round (Inversion)

2Object-generated harmful factors

If data bus inversion is applied to all signal lines, then noise is reduced, but device complexity increases due to mode selection requirements

Engineering Contradiction:
ImprovenoiseVSAvoidcircuit complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent divides the signal lines into two groups: first signal lines connected to a first latch circuit for storing current input data, and second signal lines connected to a second latch circuit for storing previous data. This segmentation allows selective application of DBI to different signal line groups based on their characteristics, reducing overall circuit complexity while maintaining noise reduction effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic mode selection where the DBI function can be selectively enabled or disabled based on operating conditions. The data bus inversion engine compares current input data with previous data and dynamically determines whether to apply inversion, allowing the system to adapt to different operating scenarios and reduce complexity by disabling DBI when not needed

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If DBI function is selectively applied based on product information, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveproduct adaptabilityVSAvoidcontrol complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements automatic mode selection where the data bus inversion circuit autonomously determines whether to enable or disable the DBI function based on product information stored in the semiconductor apparatus. The data bus inversion engine automatically compares current data with previous data and selects the appropriate mode without requiring external control signals, thereby improving adaptability while minimizing control complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12124397B2Data bus inversion circuit and semiconductor apparatus including the same
Publication Date: 2024.10.22 SK HYNIX INC
  • US12124397B2 patent drawing
  • US12124397B2 patent drawing
  • US12124397B2 patent drawing

AI summary

The present technology may include a first latch circuit configured to store, as first data, data that is transmitted through a first signal line, a second latch circuit configured to store, as a plurality of second data, the data that is transmitted through the first signal line by sorting the data by a plurality of second signal lines that are connected to the first signal line in common, and a data bus inversion engine configured to selectively perform a first mode in which the data bus inversion engine generates a data bus inversion flag by comparing the first data with current input data and a second mode in which the data bus inversion engine generates the data bus inversion flag by comparing the plurality of second data with the current input data.