Data Clock Phase Tuning for High-Speed DRAM Synchronization
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Solution Overview
Problem
Dynamic random access memory (DRAM) faces limitations in increasing data interface speed due to the fixed frequency of the main clock signal and data strobe signal, making it difficult to enhance the core operation speed while maintaining synchronization.
Innovation Solution
A semiconductor apparatus and method that tunes the phase of a data clock signal with a different frequency than the main clock signal by generating frequency-divided clock signals and comparing their phases to synchronize with the main clock signal, allowing for faster data transmission and reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the main clock signal is increased to enhance core operation speed, then the data interface speed can be improved, but it becomes very difficult to increase the speed due to the structure of the core circuit in the DRAM
Solution Approach 1:
The patent segments the clock signal handling into two independent paths: a main clock signal for core operations and a separate data clock signal for data interface operations. This allows the data interface to operate at higher frequencies independent of the core circuit's frequency limitations, resolving the contradiction by separating the constrained core operation from the flexible data transmission path.
Solution Approach 2:
The patent introduces dynamic phase tuning capability that allows the phase of the data clock signal to be adjusted based on operating conditions. This dynamic adjustment enables the system to optimize data interface timing without changing the core clock frequency, thereby improving data speed while respecting core circuit structural limitations.
2Productivity
If the data interface speed is increased by increasing the number of data bits or symbols input and output per command, then the data interface speed can be improved, but there is a limit to increasing the data interface speed with respect to the core speed of the DRAM while the main clock signal and the data strobe signal are maintained to have the same frequency
Solution Approach 1:
The patent changes the frequency parameter of the data clock signal from being equal to the main clock frequency to being a different frequency (typically twice the main clock frequency for DDR operation). This parameter change allows the data interface to transmit more data bits per command cycle without being constrained by the core speed, while the phase tuning mechanism ensures proper synchronization.
Solution Approach 2:
The patent implements dynamic phase tuning that allows the phase relationship between the data clock signal and main clock signal to be adjusted in real-time. This dynamic adaptability enables the system to maintain proper timing synchronization even when operating at different frequency ratios, removing the limitation of fixed frequency synchronization.
3Speed
If a data clock signal with a different frequency than the main clock signal is used to increase data interface speed, then the data transmission speed can be improved, but phase skew between the data clock signal and main clock signal must be reduced through tuning
Solution Approach 1:
The patent implements a feedback-based phase tuning mechanism where the phase relationship between the data clock signal and main clock signal is continuously monitored and adjusted. The phase tuner receives feedback about phase skew and dynamically adjusts the data clock phase to minimize timing errors, ensuring precise synchronization despite the frequency difference.
Solution Approach 2:
The patent performs preliminary phase tuning during initialization or mode setting before normal data operations begin. This preliminary action establishes the correct phase relationship between clocks in advance, preventing timing issues during actual data transmission and ensuring high-speed operation with proper synchronization.
Data Source
AI summary
A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.