Data Compression Test Circuit for Stacked Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor memory apparatus requires a large number of global lines for data compression and testing, especially in three-dimensional stacked configurations, leading to increased chip size, layout area, and manufacturing costs due to the need for numerous through-silicon vias (TSVs) for testing.
Innovation Solution
A semiconductor memory apparatus with a data compression test circuit that allows simultaneous compression-testing of data from multiple chips, using test signal generation units on each chip to generate and transmit test signals through TSVs, reducing the number of necessary TSVs by enabling a single TSV to handle the test results from multiple memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data compression testing is performed separately for each chip in a stacked configuration, then testing reliability is improved, but the number of TSVs required increases dramatically
Solution Approach 1:
The patent combines data from multiple memory banks across different chips and compresses them together using a single data compression circuit. Multiple determination signals from different chips are merged into a single final determination signal, reducing the number of TSVs needed while maintaining comprehensive testing coverage.
Solution Approach 2:
A single data compression circuit is designed to handle data from multiple memory banks across different chips, making it a universal testing resource. The final determination unit serves multiple chips simultaneously, eliminating the need for separate dedicated circuits for each chip.
2Reliability
If the number of global lines is increased to test more memory banks, then testing coverage is improved, but chip size and layout area increase
Solution Approach 1:
The patent merges data from multiple memory banks into a single compressed data output, allowing one global line to carry the test result for multiple banks. This consolidation reduces the number of global lines required while maintaining comprehensive testing coverage across all memory banks.
3Measurement precision
If separate test circuits are provided for each memory bank, then testing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal data compression circuit that can process data from multiple memory banks with equal accuracy. The single final determination unit maintains high measurement precision by accurately evaluating compressed data from all banks without requiring multiple specialized circuits.
4Reliability
If more TSVs are used to connect stacked chips for testing, then inter-chip connectivity is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the test signal paths from multiple chips so that a single TSV can transmit the final determination signal that represents the test results of multiple memory banks. This reduces the total number of TSVs required for inter-chip connectivity while maintaining reliable signal transmission.
Data Source
AI summary
A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test signal in response to the first and second chip test signals in the test mode.