Data Handling Circuitry Dual-Mode Online Memory Testing
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Solution Overview
Problem
Existing online circuitry testing techniques for memory devices, such as cache memories and branch predictor memories, require modifying program code or using an alternative memory during testing, which is inconvenient and disrupts normal system operation.
Innovation Solution
The implementation of data handling circuitry that can operate in both primary and secondary modes, allowing the system to transition between accessing a memory and operating independently of it, enabling online built-in self-test (MBIST) without modifying executable code, by using test circuitry to control the data handling circuitry to switch between modes during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If online testing is performed on memory devices, then testing can be done during normal operation, but the memory must be accessed by another memory or require program code changes
Solution Approach 1:
The patent introduces an intermediary mechanism (mode control logic and alternative data path) that mediates between the testing requirement and normal operation. During testing, the system switches to an alternative mode where test data paths are used instead of normal memory access paths, allowing testing without disrupting overall system function.
Solution Approach 2:
The patent implements dynamic mode switching between primary and secondary operational modes. The data handling circuitry can transition between normal operation mode and testing mode based on test initiation signals, allowing the system to adapt its configuration dynamically rather than requiring static reconfiguration or code changes.
2Reliability
If program code is modified to enable testing, then testing can be performed, but normal system operation is disrupted
Solution Approach 1:
The patent prepares alternative data handling paths and mode control mechanisms in advance during system design and initialization. When testing is initiated, the pre-configured alternative paths are activated without requiring any modification to the running program code, thus maintaining operational continuity.
Solution Approach 2:
The system performs self-testing through built-in test modes that are activated by control signals rather than external code modification. The data handling circuitry itself provides the testing capability through its dual-mode operation, eliminating the need for external testing equipment or code changes.
3Productivity
If memory is used during normal operation, then data processing functions work correctly, but testing cannot be performed without switching to alternative mode
Solution Approach 1:
The patent segments the data handling circuitry into distinct functional paths: a primary path for normal data processing and a secondary path for testing. This segmentation allows each path to operate independently, enabling testing without affecting normal data processing productivity when not in test mode.
Solution Approach 2:
The data handling circuitry is designed with multi-functionality, capable of performing both normal data processing operations and self-testing operations. The same physical circuitry serves dual purposes by switching between primary and secondary modes, eliminating the need for separate dedicated test hardware.
Data Source
AI summary
Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test operation is performed on the memory; and the test circuitry is configured to control the data handling circuitry to return to the primary mode in response to completion of the test operation on the memory.