Functional Testing TRIZ Cases
- Avionics LRU Dataload Protocol Testing via Invalid Sequence Injection
A testing system for avionics LRUs initiates dataload sequence transfers to verify hardware acceptance status and protocol handling.
- Distributed Simulation Nodes with Local Data Storage
Local data storage and updaters eliminate central bottlenecks by enabling parallel task execution without shared access delays.
- Built-in Self-test and Repair Circuit for Memory Defect Detection
A built-in self-test logic circuit identifies defective memory cells within an integrated circuit device.
- Secure Memory Test Mode Vector Filtering
A memory device restricts test mode writes to predefined vectors, converting non-matching data into valid patterns.
- Test Apparatus Control for Overlapping Test Result Processing
A test apparatus control system stores execution orders to process overlapping test results in the correct sequence.
- Debugging Unit Clock Segmentation for Low Power Microcontrollers
A debugging unit uses a separate clock signal to transmit data while the main system clock changes rate.