Built-in Self-test and Repair Circuit for Memory Defect Detection
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Solution Overview
Problem
Existing integrated circuit devices require expensive high-speed testers for manufacturing verification, limiting the application of advanced defect detection strategies and increasing manufacturing costs due to the need for specialized equipment capable of testing at high operating frequencies.
Innovation Solution
Incorporating a built-in self-test and repair circuit within the device, which includes a self-test logic circuit to identify and a self-repair logic circuit to automatically replace defective memory cells with spare cells, allowing for automated defect detection and repair without the need for external high-speed testers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external high-speed testers are used for manufacturing verification, then defect detection capability is improved, but manufacturing cost increases
Solution Approach 1:
The memory device performs self-testing through built-in test circuits that can autonomously detect defects without requiring external high-speed testers. The test circuits generate test patterns, apply them to memory cells, and detect defects internally, enabling the device to service its own testing needs and eliminate dependence on expensive external equipment.
Solution Approach 2:
The built-in test circuits are integrated into the normal memory operation infrastructure, allowing the same memory cells and circuitry to serve both as operational memory and as test subjects. This multi-functionality enables defect detection using existing device resources rather than requiring separate specialized testing equipment.
2Ease of manufacture
If built-in self-test circuits are integrated into the device, then manufacturing cost decreases, but device complexity increases
Solution Approach 1:
The test circuits are merged with the normal memory operation circuits, sharing common infrastructure such as word lines, bit lines, and memory cells. This integration allows defect detection functionality to be combined with existing memory operations, reducing the need for completely separate test circuitry and minimizing the increase in device complexity.
Data Source
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AI summary
In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.