Debugging Unit Clock Segmentation for Low Power Microcontrollers
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Solution Overview
Problem
Existing debugging systems face communication errors due to asynchronous changes in the clock rate during low power consumption modes, disrupting the debugging operation between microcontrollers and external tools.
Innovation Solution
A debugging unit with separate clock signals for system operations and debugging communications, allowing the clock rate to be adjusted independently, ensuring continuous and error-free communication by using a debug clock signal that remains active even when the system clock is stopped.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the microcontroller stops the clock signal to enter low power consumption mode, then energy consumption is reduced, but communication with the external tool is disabled and debugging operation is interrupted
Solution Approach 1:
The patent segments the clock signal system into two independent parts: a main system clock that can be stopped for power saving, and a separate background debug clock that continues running to maintain communication. This allows the microcontroller to enter low power mode while the debugging unit remains operational with its own dedicated clock signal.
Solution Approach 2:
The patent introduces a background debug system as an intermediary layer between the main CPU and the external tool. This background debug unit has its own independent clock source that operates separately from the main system clock, enabling it to mediate communication even when the main system is in low power mode.
2Adaptability or versatility
If the frequency dividing ratio of the clock control section is changed during low power consumption mode, then the clock rate adapts to application requirements, but the communication rate becomes asynchronous and communication errors occur
Solution Approach 1:
The patent implements dynamic clock rate adjustment for the background debug clock based on the main system clock's frequency dividing ratio. When the main clock changes frequency, the background debug clock automatically adjusts its division ratio to maintain synchronous communication, enabling adaptive operation without communication errors.
Solution Approach 2:
The patent employs a feedback mechanism where the background debug system monitors the main system clock's frequency changes and automatically adjusts its own clock division ratio accordingly. This feedback loop ensures that the communication rate remains synchronized with the main system even during dynamic frequency transitions.
Data Source
AI summary
An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.