Data Interface Circuit for Nonvolatile Memory Random Access

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Solution Overview

Problem

Conventional nonvolatile memory devices using the DDR method face limitations in random data input/output operations due to fixed allocation of even and odd column addresses, which restricts flexibility and efficiency in data access.

Innovation Solution

A data interface circuit and nonvolatile memory device design that separates consecutive input data into rising and falling data, allowing selective transfer to even and odd column lines based on a start column address, enabling random access during data input/output operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed allocation of even and odd column addresses is used in DDR method, then data input/output synchronization with clock edges is achieved, but random data access flexibility is restricted

Engineering Contradiction:
Improvedata input/output synchronizationVSAvoidrandom data access flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the column address allocation flexible rather than fixed. The control logic dynamically determines whether to allocate even column addresses to rising data or falling data based on the least significant bit of the start column address. This dynamic allocation allows the system to adapt to different access patterns while maintaining DDR synchronization, thereby resolving the contradiction between reliability and adaptability.

Inventive Principle:
Principle #15Dynamics

2Reliability

If consecutive input data are separated into rising and falling data with fixed column line allocation, then DDR synchronization is maintained, but data access efficiency is reduced

Engineering Contradiction:
ImproveDDR synchronizationVSAvoiddata access efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The control logic dynamically selects which data group (rising or falling) is allocated to which column line based on the start column address. When the least significant bit is 0, rising data goes to even column lines and falling data to odd column lines. When the least significant bit is 1, the allocation is reversed. This dynamic allocation optimizes data access efficiency while maintaining DDR synchronization.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the allocation parameter (which data group maps to which column line) based on the start column address value. This parameter change allows the system to adapt to different access scenarios, improving data access efficiency without compromising the DDR synchronization mechanism.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8553477B2Data interface circuit, nonvolatile memory device including the same and operating method thereof
Publication Date: 2013.10.08 SK HYNIX INC
  • US8553477B2 patent drawing
  • US8553477B2 patent drawing
  • US8553477B2 patent drawing

AI summary

A data interface unit is used in a semiconductor memory device and includes a data alignment unit configured to separate consecutive input data into rising data and falling data, and a data transfer unit configured to selectively transfer the rising data and falling data to an even column line and an odd column line in response to a start column address.