Data Inversion Detection Circuit for High-Speed Memory
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Solution Overview
Problem
Existing data bus inversion (DBI) schemes face challenges in efficiently detecting and managing data inversion in memory circuits, leading to increased power consumption and noise due to simultaneous switching, particularly in high-speed applications like SRAM and DRAM, where accurate bit detection is crucial.
Innovation Solution
The implementation of a data inversion detection circuit comprising a transistor array, bias generator, and sense amplifier, which utilizes complementary transistors and biasing to detect bit inversion and generate an inversion flag, allowing for high-speed and power-efficient data inversion management by determining whether data should be inverted during write operations and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data bus inversion is implemented to reduce simultaneous switching noise and power consumption, then AC power consumption and switching noise are reduced, but device complexity increases due to the need for detection circuits and inversion logic
Solution Approach 1:
The detection circuit automatically monitors the data bus state and generates inversion control signals without external intervention. The circuit self-determines when inversion is needed based on the number of logic 1s detected, eliminating the need for external control logic and reducing overall system complexity despite adding detection functionality.
Solution Approach 2:
The system dynamically changes the inversion state parameter based on detected data patterns. When the number of logic 1s exceeds a threshold (e.g., 5 bits), the inversion control signal toggles to invert the data bus, thereby reducing the number of simultaneous switching transitions and lowering AC power consumption.
2Object-generated harmful factors
If data bus inversion is implemented to reduce simultaneous switching noise, then switching noise is reduced, but device complexity increases due to additional detection and control circuitry
Solution Approach 1:
The detection circuit automatically monitors the data bus state and generates inversion control signals without external intervention. The circuit self-determines when inversion is needed based on the number of logic 1s detected, eliminating the need for external control logic and reducing overall system complexity despite adding detection functionality.
Solution Approach 2:
The system dynamically changes the inversion state parameter based on detected data patterns. When the number of logic 1s exceeds a threshold (e.g., 5 bits), the inversion control signal toggles to invert the data bus, thereby reducing the number of simultaneous switching transitions and lowering switching noise.
3Speed
If faster bit detection is implemented to support high-speed applications, then clock frequency support increases, but power consumption increases due to faster switching and higher current draw
Solution Approach 1:
The detection circuit uses a simplified counting approach that stops detecting once a threshold is reached, rather than counting all bits. This partial action approach provides sufficiently fast detection for high-speed applications while limiting the duration and intensity of switching activity, thereby controlling power consumption.
Solution Approach 2:
The circuit optimizes detection speed by adjusting the threshold parameter and using fast-switching transistors configured for rapid state changes. The detection logic is designed to reach a decision state quickly when the number of logic 1s crosses the threshold, enabling support for high clock frequencies while minimizing the time window for power-consuming switching operations.
Data Source
AI summary
Systems and methods of data inversion, circuitry, detection and/or schemes are disclosed. According to illustrative implementations, exemplary circuitry may include static detection or detection circuitry such as those involving static current sources to detect a threshold for data inversion, pre-conditioning of detection circuitry, and/or active detection circuitry or schemes. In some implementations, exemplary memory or data inversion circuitry may comprise a transistor array, a bias generator, and a sense amplifier, wherein the transistor array may comprise at least one pair of transistor circuits arranged so that an output of the transistor array is provided as a sum or function of signal/current outputs of at least some of the transistor circuits in the array. As set forth, various systems, methods and circuitry herein may posses only a 3 static gate delay, such that very high speed and/or fast flow-through is achieved.