Data Recovery Circuit Using 3/4-Step Oversampling
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Solution Overview
Problem
Conventional clock and data recovery circuits employing three times oversampling architectures face challenges in distinguishing data skews close to half a step, leading to errors in data recovery, and require complex circuit layouts with numerous sampling clocks, increasing area and cost.
Innovation Solution
The implementation of a data recovery apparatus and method using three quarter steps oversampling, which replaces the phase selecting architecture with a delay selecting architecture, reducing the number of sampling clocks and improving tolerance to the eye diagram of input data, thereby simplifying the circuit layout and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three times oversampling architecture is used to recover input data, then data recovery reliability is improved by preventing errors induced by skews, but device complexity increases due to requiring 21 sampling clocks with different phases and complex circuit layout
Solution Approach 1:
The patent changes the oversampling parameter from 3 times to 3 quarter steps times, which fundamentally alters the sampling clock requirements. This parameter change reduces the number of sampling clocks from 21 to 7 different phases, thereby reducing circuit complexity while maintaining the ability to recover data accurately by preventing errors induced by skews between clock and data signals.
2Manufacturing precision
If three times oversampling architecture is used to ensure correct data recovery, then manufacturing precision is improved, but the area of circuit layout increases due to complex architecture
Solution Approach 1:
By changing the oversampling parameter to 3 quarter steps times, the patent reduces the number of sampling clocks required, which directly reduces the circuit layout area. The invention maintains data recovery accuracy by using the reduced set of 7 sampling clocks with different phases to still capture sufficient sampling points for accurate data reconstruction.
Solution Approach 2:
The patent segments the sampling process into 7 distinct phases instead of 21 phases, dividing the oversampling operation into fewer but more strategically positioned sampling events. This segmentation reduces the overall circuit area required while maintaining the necessary sampling density for accurate data recovery.
3Reliability
If phase selecting architecture is used in conventional data recovery circuits, then data recovery is achieved, but device complexity increases and costs increase due to requiring numerous sampling clocks
Solution Approach 1:
The patent introduces a delay selecting architecture that changes the operational parameter from phase selection among 21 clocks to delay selection among 7 clocks. This architectural change maintains data recovery capability while reducing complexity by using fewer sampling clocks with different phases, thereby simplifying the overall system design.
Data Source
AI summary
A data recovery apparatus and method for receiving at least an original clock and at least an original data stream output from a transmitter to output at least one recovery data are provided. The original data stream and the recovery data respectively include N steps in a period T of the original clock, wherein N is an integer larger than 0. The data recovery apparatus includes a sampling unit and a processing unit. The sampling unit samples the original data stream according to the original clock, wherein the sampling unit samples the corresponding data of the original data stream at least three times with T/(4N) sample period in each step. The processing unit receives and compares the sampled result output from the sampling unit, and recovers the sampled result to the recovery data according to the compared result.