Data Storage Bit Line Formation via Segmented Trench Patterning
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Solution Overview
Problem
As semiconductor data storage devices become more highly integrated, their reliability is compromised, necessitating improved manufacturing methods to enhance process margins and maintain high performance.
Innovation Solution
A method for manufacturing data storage devices involving the formation of alternately arranged first and second trenches, bit lines, and interconnections, with specific height and width configurations, and the use of conductive layers to ensure reliable and efficient data storage element formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data storage devices are highly integrated to reduce size and cost, then manufacturing complexity and reliability deterioration increase
Solution Approach 1:
The patent divides the bit line formation process into multiple stages: first bit lines are formed in first trenches, then second bit lines are formed in second trenches that are patterned between the first bit lines. This segmentation allows each trench type to be optimized independently, maintaining reliability while achieving high integration through alternating arrangement of first and second bit lines.
Solution Approach 2:
The patent introduces vertical dimension control by forming second trenches at different depths than first trenches, with second bit lines having different top and bottom surface heights compared to first bit lines. This multi-level three-dimensional arrangement increases integration density while maintaining sufficient spacing and process margins for reliable manufacturing.
2Productivity
If element widths and spaces are reduced to increase integration, then manufacturing precision requirements increase
Solution Approach 1:
The patent segments the trench formation into distinct first trenches and second trenches with different patterning steps. First trenches are patterned initially, then second trenches are patterned between them in a subsequent step. This segmentation allows each etching process to be independently optimized with appropriate process margins, reducing the cumulative precision requirements compared to forming all trenches in a single step.
Solution Approach 2:
The patent performs preliminary patterning of first trenches and first bit lines before forming second trenches and second bit lines. This preliminary action establishes a foundation structure that guides subsequent patterning steps, allowing for better control of feature dimensions and spacing while maintaining process flexibility for achieving high integration density.
3Productivity
If multiple bit lines are formed simultaneously to increase productivity, then process control and reliability decrease
Solution Approach 1:
The patent segments bit line formation into sequential batches: first bit lines are formed in first trenches, then second bit lines are formed in second trenches. Each batch can be processed with dedicated process parameters and quality control measures, ensuring reliable process control while maintaining high overall productivity through the alternating arrangement that allows parallel processing of different trench types.
Solution Approach 2:
The patent performs preliminary formation of first bit lines before forming second bit lines. This preliminary action allows process parameters, materials, and quality control procedures to be established and validated in the first batch, then applied and refined for the second batch, ensuring consistent process control across multiple production cycles.
Data Source
AI summary
Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.