Data Strobe Encoding Circuit Using XOR Clock Generation
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Solution Overview
Problem
Conventional data/strobe encoding schemes face challenges in ensuring sufficient setup time for data decoding, particularly when the strobe signal does not change, leading to incorrect data decoding and increased design and production costs due to the need for device-specific delay circuits in Large Scale Integration (LSI) systems.
Innovation Solution
A data/strobe encoding scheme circuit that uses separate lines for data and strobe signals, employing a clock generator, clock enable generator, flip-flop enable flag generator, meta-stable countermeasure circuits, and a command decoder to manage latching and decoding operations independently of LSI device characteristics, eliminating the need for device-specific delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay control circuit including an analog circuit adopting a delay element is adopted to provide setup time for data, then the setup time for data is sufficient, but the designing period of time is elongated and production cost increases
Solution Approach 1:
The patent replaces the mechanical/analog delay element circuit with a digital logic-based delay mechanism. The delay is achieved through logical operations (XOR between data and strobe) and digital signal processing in the flip-flop circuit, eliminating the need for physical delay elements and analog circuits. This substitution reduces design complexity and production costs while maintaining the required setup time.
Solution Approach 2:
The patent changes the approach from fixed analog delay to dynamic digital delay control. The delay timing is controlled by the clock signal generated from the XOR operation between data and strobe signals, allowing the delay parameter to be adjusted through digital logic rather than physical circuit modification. This enables flexible timing control without redesigning the delay circuit for each device characteristic.
2Reliability
If a delay control circuit including an analog circuit adopting a delay element is adopted to provide setup time for data, then the setup time for data is sufficient, but production cost increases
Solution Approach 1:
The patent replaces expensive analog delay elements and dedicated LSI circuits with standard digital logic components. The delay function is implemented using common digital circuits (XOR gates, flip-flops) that are already part of standard LSI fabrication processes, eliminating the need for specialized analog components and reducing production costs.
Solution Approach 2:
The patent makes the delay control mechanism universal by using the same XOR-based clock generation approach for all devices, regardless of specific LSI characteristics. This eliminates the need for device-specific delay circuit design and allows standardization across production, reducing manufacturing costs through economies of scale.
3Loss of information
If the conventional art is used to decode command including last bit, then data decoding can be completed, but the setup time is insufficient and data is not correctly decoded
Solution Approach 1:
The patent performs preliminary actions by generating the clock signal through XOR operation between data and strobe before the actual latching operation. This preliminary clock generation ensures that the timing relationship is established in advance, providing sufficient setup time for the flip-flop to correctly latch the data including the last bit of the command.
Solution Approach 2:
The patent uses feedback from the strobe signal to dynamically control the clock timing. The XOR operation between data and strobe creates a clock signal that automatically adjusts to ensure proper timing margins, providing feedback-based timing control that guarantees sufficient setup time for accurate data decoding.
Data Source
AI summary
In a data/strobe encoding scheme circuit in which data and a strobe signal are transmitted through different lines, changes respectively in the data and the strobe signal are employed as clock signals for a latching operation, and the data is transmitted to a succeeding-stage circuit operating on a second clock signal. The circuit latches predetermined data by an FF circuit and passes a data pair including a signal indicating that the data has been latched and held therein as well as the latched data to the succeeding-stage circuit, activates, if assertion of a signal indicating reception of the data is received from the succeeding-stage circuit, again the FF circuit which has latched the data and has entered a stop state, and receives new data. There is provided a data/strobe encoding scheme circuit and a data/strobe encoding method, it is possible to implement a data/strobe encoding scheme circuit and a data/strobe encoding method capable of realizing a low-cost data/strobe encoding scheme which is independent of LSI device characteristics and which can be easily designed.