Dataflow Processor Architecture for Dark Silicon Management
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Solution Overview
Problem
The disparity between shrinking transistor dimensions and non-shrinking supply voltage leads to a 'dark silicon' issue, where only a fraction of general-purpose processors can be powered on under a given power budget, necessitating either reduced circuit utilization or increased power consumption, especially in general-purpose processors.
Innovation Solution
A dataflow-based general-purpose processor architecture that dynamically maps a dataflow graph in hardware using feedforward register lanes, allowing instructions to be executed concurrently and reusing the constructed datapath, thereby improving energy efficiency and supporting existing instruction sets without requiring new compilers or libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor dimensions are scaled down to improve processing density, then circuit utilization increases, but supply voltage cannot be scaled proportionally leading to power budget constraints
Solution Approach 1:
The processor dynamically reconfigures its datapath at runtime based on the characteristics of the running workload. The system switches between different operational modes (e.g., scalar mode, vector mode, matrix mode) to optimize performance for specific tasks, allowing the hardware to adapt its structure dynamically rather than being fixed
Solution Approach 2:
The processor implements a unified architecture that can perform multiple functions including scalar operations, vector operations, and matrix operations within the same hardware structure. This multi-functionality allows a single processor to handle diverse workloads efficiently without requiring separate specialized units for each operation type
2Productivity
If more processing elements are activated to improve performance, then processing speed increases, but power consumption exceeds the power budget creating dark silicon
Solution Approach 1:
The processor is divided into multiple independently controllable processing elements including scalar units, vector units, and matrix units. Each segment can be independently activated or deactivated based on the requirements of the current workload, allowing fine-grained power management where only necessary processing elements are powered on
Solution Approach 2:
The processor periodically reevaluates the characteristics of the running workload and dynamically switches between different operational modes and activates/deactivates processing elements accordingly. This periodic adaptation ensures that the processor maintains optimal performance while staying within power budget constraints by adjusting its active components based on current task requirements
3Use of energy by moving object
If dynamic reconfiguration is implemented to improve energy efficiency, then power consumption decreases, but hardware complexity increases
Solution Approach 1:
The processor merges multiple functional units (scalar, vector, matrix) into a single unified architecture with shared resources such as register files and interconnect structures. This consolidation reduces the overall hardware complexity compared to having completely separate dedicated units for each operation type, while still enabling dynamic reconfiguration through mode switching
Data Source
AI summary
A dataflow-based general-purpose processor architecture and its method are disclosed. A circuit for the dataflow-based general-purpose processor architecture includes multiple processing elements (PEs) corresponding to multiple assigned central processing unit (CPU) instructions in program order, a register file, and multiple feedforward register lanes configured to map each of the multiple assigned CPU instructions on the multiple PEs to the register file or another PE of the multiple PEs to construct a hardware datapath corresponding to a dataflow graph of the multiple assigned CPU instructions. Other aspects, embodiments, and features are also claimed and described.