Interdigitated DC Link Bus for Power Converter Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DC link buses in power converter systems face limitations in reducing inductance between positive and negative bus bars, which restricts the switching speed of solid state commutation devices, leading to inefficiencies in power conversion.
Innovation Solution
The use of a DC link bus configuration with interdigitally arranged parallel planar conductive layers separated by insulation layers reduces inductance between the positive and negative bus bars, enhancing capacitance and enabling faster commutation speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DC link bus configuration is used, then manufacturing is simpler, but inductance between positive and negative bus bars is higher, limiting switching speed
Solution Approach 1:
The patent transitions from conventional single-plane bus bar arrangement to a multi-layer planar configuration with conductive layers stacked in the vertical dimension. This dimensional change allows for reduced loop area and lower inductance while maintaining a compact form factor, enabling switching speeds exceeding 200 KHZ without excessive structural complexity
Solution Approach 2:
The DC link bus is segmented into multiple conductive layers (first set and second set of parallel planar conductive layers) separated by insulation layers. This segmentation allows optimization of current paths in each layer to minimize inductance, while the modular layered structure keeps manufacturing complexity manageable through standardized assembly processes
2Productivity
If inductance is reduced to increase switching speed, then power conversion efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
Insulation layers are introduced as intermediary elements between the first and second sets of parallel planar conductive layers. These insulation layers serve dual purposes: electrically isolating adjacent conductive layers while providing mechanical spacing that defines the geometric parameters for inductance reduction. The insulation layers act as mediators that enable precise control of layer spacing without requiring direct metal-to-metal positioning, thereby reducing manufacturing precision requirements
Solution Approach 2:
The patent optimizes the spacing between conductive layers and the dimensions of parallel planar conductive layers to achieve target inductance values. By carefully controlling geometric parameters (layer spacing, layer length, layer width) within reasonable tolerances, the design achieves low inductance for high efficiency power conversion while maintaining manufacturability through standard precision capabilities
3Speed
If interdigitally arranged parallel planar conductive layers are used, then inductance is reduced and switching speed increases, but device complexity increases
Solution Approach 1:
The multi-layer planar conductive structure serves multiple functions simultaneously: it provides electrical connectivity for DC link current, establishes magnetic coupling for inductance reduction, and creates a compact integrated assembly that eliminates the need for separate stacked capacitors. This multi-functionality justifies the increased structural complexity by delivering superior performance in switching speed and power conversion efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for higher power conversion efficiency and faster switching speeds of solid state commutation devices, potentially exceeding 200 KHZ, while reducing manufacturing costs and eliminating the need for stacked capacitors.
Implementation Method 1
a set of insulation layers separating each of the first set of parallel planar conductive layers from the adjacent second set of parallel planar conductive layers by a length in the first direction. The length is configured to reduce an inductance between the conductive positive link connector and the conductive negative link connector
Data Source
AI summary
A DC link bus includes a first and second set of conductive layers, arranged between insulation layers that separate the first set from the second set. A set of positive and negative link conductors are coupled normal to a respective set of conductive layers, and coupled together to define a respective positive bus and a negative bus. Additionally, a method of forming a DC link bus includes respectively coupling a first and a second set of parallel conductive layers to each other. Coupling a set of positive link connectors, and a set of negative link connectors, perpendicular to the first set and second set of layers, respectively, and to each other to define a positive bus and a negative bus. Interdigitally arranging the first and second set of conductive layers, spacing adjacent layers of the second set of layers to reduce an inductance between the positive and negative bus.