Charge-Sharing DCO Locking for PLL Phase and Frequency Error Control
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Solution Overview
Problem
Phase locked loops (PLLs) face challenges in reducing phase jitter and frequency errors in high-frequency signal generation due to limitations in existing charge-sharing correction methods, which affect the accuracy and stability of oscillating signals in digital communication systems and radio frequency applications.
Innovation Solution
A ring-based digitally controlled oscillator (DCO) coupled with a charge-sharing circuit that includes a charge-sharing capacitor, switch, and digital-to-analog converter (DAC), where the charge on the capacitor is shared with the node-to-ground capacitor at specific times to correct phase errors, changing the closed-loop transfer function of the PLL from type-II to type-I during charge-sharing correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If charge-sharing correction is applied to reduce phase jitter, then phase accuracy is improved, but the closed-loop transfer function changes from type-II to type-I which may reduce frequency accuracy
Solution Approach 1:
The charge-sharing correction is applied at specific predetermined timing points before the phase error accumulates significantly. By performing the charge-sharing operation at optimally selected moments in the oscillation cycle, the system proactively corrects phase deviations while maintaining frequency stability through the preliminary nature of the correction.
Solution Approach 2:
The charge-sharing correction is applied periodically at regular intervals synchronized with the oscillation cycle of the DCO. This periodic application ensures that phase corrections are made consistently without disrupting the overall frequency stability, as the corrections occur at predictable moments that do not interfere with the fundamental oscillation frequency.
2Measurement precision
If charge-sharing correction is applied frequently, then phase jitter reduction is improved, but power consumption and circuit complexity increase
Solution Approach 1:
Instead of applying charge-sharing correction at every possible moment, the system applies it only at specific predetermined timing points where it is most effective. This partial application approach achieves sufficient phase jitter reduction without the excessive complexity and power consumption that would result from continuous or overly frequent corrections.
Solution Approach 2:
The system performs charge-sharing correction only when predetermined conditions are met, rather than continuously monitoring and correcting phase errors. This selective preliminary correction approach reduces the operational complexity of the charge-sharing circuit while maintaining effective phase jitter reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces phase and frequency errors by correcting oscillating signals, improving the accuracy and stability of the output signal, and enhancing the performance of PLLs in generating high-frequency signals for various applications.
Implementation Method 1
the charge on the capacitor is shared with the node-to-ground capacitor at specific times to correct phase errors
Data Source
AI summary
An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.