Digitally Controlled Oscillator Layout for Parasitic Inductance Isolation
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Solution Overview
Problem
Conventional Digitally Controlled Oscillators (DCOs) in Phase-Locked Loops (PLLs) suffer from parasitic inductance issues that invalidate calibration due to lock-state dependency between compensation and modulation capacitor banks, leading to degraded chirp linearity and frequency errors.
Innovation Solution
The DCO is arranged in a star configuration where modulation capacitor banks are connected to a negative transconductance stage via separate paths from compensation capacitor banks, reducing parasitic inductance and mitigating lock-state dependency, thereby maintaining calibration integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If modulation capacitor banks and compensation capacitor banks are connected through common paths in conventional DCOs, then device complexity is reduced, but parasitic inductance increases causing calibration invalidation and frequency errors
Solution Approach 1:
The patent segments the capacitor bank connections by providing separate paths: a first path for modulation capacitor banks and a second path for compensation capacitor banks. This segmentation isolates the modulation capacitor banks from parasitic inductance introduced by compensation capacitor bank connections, thereby maintaining calibration integrity while managing device complexity.
Solution Approach 2:
The patent introduces separate connection paths as intermediary structures between the capacitor banks and the resonant circuit. These separate paths act as mediators that prevent the direct coupling of parasitic inductance from compensation capacitor banks to the modulation capacitor banks, thus protecting the calibration of the modulation capacitors.
2Ease of manufacture
If compensation capacitor banks are connected to modulation capacitor banks through common paths, then ease of manufacture is improved, but lock-state dependency invalidates calibration leading to degraded chirp linearity
Solution Approach 1:
The patent divides the connection topology into separate segments: modulation capacitor banks connect through a first path while compensation capacitor banks connect through a second path. This segmentation ensures that manufacturing variations in one path do not affect the calibration of capacitor banks in the other path, thereby maintaining chirp linearity precision.
Solution Approach 2:
The patent applies local quality by providing different connection paths with different characteristics: the first path is optimized for modulation capacitor banks to minimize parasitic inductance impact on calibration, while the second path is optimized for compensation capacitor banks. This localized optimization maintains high chirp linearity despite manufacturing variations.
3Reliability
If separate paths are provided for modulation and compensation capacitor banks, then parasitic inductance impact is reduced improving calibration stability, but device complexity increases
Solution Approach 1:
The patent implements segmentation by creating separate connection paths for modulation and compensation capacitor banks. This segmentation isolates the modulation capacitor banks from parasitic inductance, ensuring calibration stability and reliability, while the modular nature of the segmentation keeps the added complexity manageable.
Solution Approach 2:
The patent extracts the modulation capacitor banks from the common connection path that introduces parasitic inductance. By taking out the modulation capacitor banks and providing them with a dedicated first path, the patent eliminates the source of calibration instability while adding only the necessary minimal complexity for the separate connection.
4Device complexity
If modulation capacitor banks are subject to parasitic inductance from compensation capacitor banks, then device complexity is reduced, but frequency accuracy deteriorates due to calibration invalidation
Solution Approach 1:
The patent introduces separate connection paths as intermediary structures that prevent parasitic inductance from compensation capacitor banks from affecting modulation capacitor banks. This intermediary structure preserves frequency accuracy by maintaining calibration validity, while the implementation remains integrated within the existing DCO architecture.
Solution Approach 2:
The patent segments the electrical connections to create isolated paths: the first path for modulation capacitor banks is separated from the second path for compensation capacitor banks. This segmentation prevents the degradation of frequency accuracy by eliminating the parasitic inductance coupling while maintaining a relatively simple overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement enhances chirp linearity and robustness by minimizing the impact of parasitic inductance on modulation capacitor banks, ensuring stable frequency modulation and improved accuracy in PLL operations.
Implementation Method 1
a negative transconductance stage coupled to a first node, a second node, and a reference node
Implementation Method 2
a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting the first node to a first output node, and the second path connecting the second node to a second output node
Data Source
AI summary
The present disclosure relates to an oscillator, such as a Digitally Controlled Oscillator (DCO), having first capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node, and second capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second capacitor banks including at least one modulation capacitor bank