Double Data Rate ADC Comparator for Low-Power Wideband Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern mobile communication devices require energy-efficient wide bandwidth analog to digital converters (ADCs) that are sensitive to variations in temperature and manufacturing processes, and traditional delta-sigma ADCs with high order loop filters consume high power and are sensitive to excess loop delay.
Innovation Solution
A double data rate interpolating analog to digital converter that operates on both edges of a clock cycle, using a comparator core with PMOS and NMOS differential amplifier stages and a set-reset flip-flop circuit to reduce power consumption and area, while maintaining high resolution and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high order loop filter with low resolution quantization is used, then dynamic range is improved, but power consumption increases
Solution Approach 1:
The patent changes the resolution parameter of the quantizer from low (1-4 bits) to high (6 bits or more), and simultaneously changes the order of the loop filter from high to low, achieving a trade-off that reduces power consumption while maintaining dynamic range through the higher resolution quantization
Solution Approach 2:
The patent segments the quantization process into multiple stages using interpolation and folding techniques, where a 6-bit or higher resolution quantizer is implemented through systematic segmentation that enables energy efficient operation with lower order loop filter
2Measurement precision
If high order loop filter is used, then dynamic range is improved, but area increases
Solution Approach 1:
The patent changes the order parameter of the loop filter from high to low, and compensates for the reduced filtering capability by implementing higher resolution quantization (6 bits or more), thereby reducing the area occupied by the loop filter while maintaining dynamic range
Solution Approach 2:
The quantization process is segmented into multiple stages using interpolation and folding techniques, allowing the system to achieve high resolution conversion with a lower order loop filter that occupies less area
3Measurement precision
If high order loop filter is used, then dynamic range is improved, but sensitivity to variations increases
Solution Approach 1:
The patent changes the order of the loop filter from high to low, reducing the filter's sensitivity to excess loop delay and variations in temperature and manufacturing processes, while maintaining dynamic range through higher resolution quantization (6 bits or more)
Solution Approach 2:
The patent uses a lower order loop filter that is less sensitive to process variations and environmental conditions, trading off some filtering capability for improved robustness and reduced sensitivity to manufacturing variability
4Quantity of substance
If interpolation and folding techniques are used, then comparator number is reduced, but circuit complexity increases
Solution Approach 1:
The patent segments the quantization process into multiple stages using interpolation and folding techniques, where the analog input signal is folded multiple times through interpolation before being converted to digital, thereby reducing the number of comparators needed while achieving high resolution conversion
Solution Approach 2:
The patent introduces time-based interpolation that operates in the time domain, adding a temporal dimension to the conversion process where signals are interpolated in time before folding, thereby reducing the spatial complexity (number of comparators) while maintaining high resolution
Data Source
AI summary
A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.