DDR Data Input Circuit Strobe Signal Edge Detection
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Solution Overview
Problem
DDR synchronous memory devices experience errors during write operations due to ringing in the data strobe signal during the postamble period, which can cause valid data to be overwritten with invalid data.
Innovation Solution
A data input circuit is designed with a data alignment unit, a data strobe signal detection circuit, and a data latch unit to align and latch internal data in synchronization with both rising and falling strobe signals, and a write latch signal is generated to prevent errors by detecting the last falling edge of the data strobe signal and using a final clock to ensure accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data strobe signal is used to latch internal data during write operations, then data transfer speed is improved, but ringing in the data strobe signal during postamble period causes valid data to be overwritten with invalid data
Solution Approach 1:
The patent applies preliminary action by generating the write latch signal in advance based on detecting the last falling edge of the data strobe signal. This ensures that the data latch unit is prepared to latch data at the appropriate timing, preventing overwriting by invalid data while maintaining high-speed operation. The write latch signal is generated before the actual data latching occurs, allowing the system to anticipate and prevent the ringing-induced error.
2Productivity
If multi-bit prefetch method is used to increase bandwidth, then data processing capability is improved, but ringing in data strobe signal causes errors in write operations
Solution Approach 1:
The patent implements feedback by using the data strobe signal itself to generate the write latch signal through detection of the last falling edge. This feedback mechanism ensures that the data latching timing is dynamically adjusted based on the actual state of the data strobe signal, preventing errors caused by ringing while maintaining the high bandwidth capability of the multi-bit prefetch method.
3Measurement precision
If data is latched in synchronization with rising and falling edges of data strobe signal, then data alignment is improved, but ringing causes invalid data to be latched
Solution Approach 1:
The patent applies preliminary action by generating the write latch signal in advance based on detecting the last falling edge of the data strobe signal. This ensures that the data latch unit is prepared to latch data at the appropriate timing, preventing overwriting by invalid data while maintaining high-speed operation. The write latch signal is generated before the actual data latching occurs, allowing the system to anticipate and prevent the ringing-induced error.
Data Source
AI summary
A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.