DDR Data Latch Clock Phase Control Using Variable Delay
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Solution Overview
Problem
In DDR synchronous semiconductor apparatuses, precise latching of external data requires precise control of the data latch clock signal's phase, but existing technologies struggle to maintain a stable phase difference of 90 degrees between external data and the clock signal, leading to errors in data reception.
Innovation Solution
A semiconductor apparatus with a variable delay unit, delay amount control unit, and data receiver that generates a data latch clock signal by calculating and converting phase codes from external data and clock signal phases, allowing for precise synchronization and phase adjustment to achieve a 90-degree phase difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data receiver latches external data in synchronization with clock signal, then data reception speed is improved through DDR synchronous operation, but phase stability between external data and data latch clock signal deteriorates, leading to latching errors
Solution Approach 1:
The patent implements a feedback mechanism where the phase detection unit continuously monitors the phase relationship between external data and data latch clock signal, and the delay amount control unit adjusts the variable delay unit based on this feedback to maintain optimal 90-degree phase difference. This closed-loop control ensures reliable data latching while operating at high DDR speeds.
Solution Approach 2:
The patent employs dynamic phase adjustment by making the delay amount of the reference clock signal variable rather than fixed. The variable delay unit can dynamically change its delay amount in response to phase detection results, allowing the system to adapt to varying operating conditions and maintain synchronization accuracy at high speeds.
2Device complexity
If fixed delay unit is used to generate data latch clock signal, then device complexity is reduced, but manufacturing precision of phase difference deteriorates, causing inaccurate data latching
Solution Approach 1:
The patent changes the parameter of delay amount from fixed to variable. By introducing a variable delay unit controlled by delay codes generated from phase detection, the system achieves precise 90-degree phase difference control without requiring complex fixed delay circuitry designed for specific timing conditions.
Solution Approach 2:
The patent segments the phase control function into distinct modules: phase detection unit, delay amount control unit, and variable delay unit. This segmentation allows each module to perform its specific function optimally while maintaining overall system manageability and reducing design complexity compared to a monolithic fixed delay approach.
Data Source
AI summary
A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.