DDR SDRAM Timing Margin Extension via Data Strobe Relay
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Solution Overview
Problem
The existing methods for writing data to DDR SDRAM arrays face challenges in maintaining a sufficient timing margin due to narrow data valid windows, making it difficult to capture data accurately under process, temperature, and voltage variations, and failing to meet JEDEC timing requirements.
Innovation Solution
The method involves providing a data strobe signal with a transition edge corresponding to the clock signal's transition edge, allowing for data relay based on the clock signal if the data strobe signal arrives earlier, thereby increasing the timing margin by extending the data valid window from ½ to ¾ clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to DDR SDRAM array using conventional timing methods, then data can be captured at the clock edge, but the timing margin is insufficient due to narrow data valid windows
Solution Approach 1:
The patent applies preliminary action by using the data strobe signal to indicate data availability before the actual data capture occurs. The strobe signal transitions in advance to prepare the memory circuitry for incoming data, allowing the data to be valid and ready before the clock edge arrives, thus increasing the timing margin for reliable data capture
2Reliability
If data valid window is extended to increase timing margin, then data capture reliability improves under PVT variations, but the conventional method only provides ½ clock cycle window
Solution Approach 1:
The patent introduces an intermediary element - the data strobe signal - that mediates between the data signal and the clock signal. The strobe signal acts as a intermediary indicator that prepares the system for data arrival, extending the valid window from ½ to ¾ clock cycle while maintaining clear timing relationships without excessive complexity
3Loss of time
If data strobe signal arrives earlier than clock signal, then timing margin can be increased, but data must be relayed based on clock signal transition edge
Solution Approach 1:
The patent employs feedback by using the clock signal's transition edge to control the relaying of data that was indicated by the earlier data strobe signal. The clock edge provides feedback control to ensure data is relayed at the correct moment, synchronizing the data transfer while maintaining the extended timing margin benefit
Data Source
AI summary
A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.