DDR SDRAM Scan Testing Controller Background Operation
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Solution Overview
Problem
Conventional defect mapping processes in memory devices monopolize the memory during testing, preventing their use during runtime and thus cannot be performed in operational environments without disrupting other applications.
Innovation Solution
An automated scan test system for DDR SDRAM that operates in the background, using a controller with a control state machine, test state machine, and configuration registers to perform incremental test scans on memory segments without interfering with ongoing operations, allowing for continuous use of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional defect mapping process is used to test memory devices, then defects can be detected and mapped, but the memory device is fully monopolized during testing and cannot be used for other applications
Solution Approach 1:
The memory device is divided into a test region and a non-test region. The test region is further segmented into multiple memory segments that can be tested incrementally. This segmentation allows the defect mapping process to operate on only a portion of the memory at any given time, leaving other regions accessible for normal operations.
Solution Approach 2:
The defect mapping process is implemented as a periodic background task that executes in intervals rather than continuously monopolizing the memory. The control state machine performs test scans periodically and waits between individual test scans, allowing other applications to access the memory during non-testing periods.
2Reliability
If a defect mapping process monopolizes the memory device during testing, then comprehensive defect detection is achieved, but continuous operation and runtime testing are prevented
Solution Approach 1:
Instead of testing the entire memory device in a single monopolizing operation, the system performs partial testing by dividing the memory into multiple segments and testing them incrementally. The control state machine can test one segment at a time or repeat tests on the same segment multiple times, achieving thorough defect detection without requiring complete memory monopolization at any moment.
Solution Approach 2:
The system performs preliminary defect mapping during manufacturing or initialization phases, establishing a baseline defect map before runtime. This preliminary action allows the memory to be fully utilized during normal operations while still maintaining defect awareness, and enables optional runtime re-testing without disrupting established operations.
3Ease of operation
If incremental test scans are performed on memory segments, then runtime testing becomes possible, but test duration and complexity increase
Solution Approach 1:
The incremental test scans are organized as periodic operations where the control state machine tests one or more memory segments, then waits before proceeding to the next segment or repeating tests. This periodic approach distributes the total test time across multiple intervals, making runtime testing feasible without requiring continuous monopolization of the memory device.
Data Source
AI summary
A controller for scan testing a memory. The controller includes a control state machine for controlling the scan process, a test sequence stored in a random access memory used by the control state machine for controlling an actual memory test, a pattern generation data unit responsive to the control state machine for generating a test pattern that is written to and read from a memory under test, a configuration register read by the control state machine for configuring the controller and a fault location register written to by the control state machine for storing locations of defects in the memory. The controller is used to auto scan a memory in real time, interleaved with other processes accessing the memory. The controller has several modes of operation including operating in a periodic burst mode to conserve power and in a background mode so as not to interfere with other processes accessing the scanned memory.