DDR Test Controller Pad Reuse for Memory Cost Reduction
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Solution Overview
Problem
The existing memory device testing processes are costly due to the need for multiple pads, particularly the data strobe (DQS) pad, which increases the manufacturing cost of test devices, especially during double data rate (DDR) tests.
Innovation Solution
Incorporating a DDR test controller that generates internal write enable and data strobe signals from existing pads, allowing the DDR test to be performed without the data strobe pad, thereby reducing the number of pads required and the manufacturing cost of test devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a data strobe pad is used for DDR testing, then DDR test functionality is achieved, but manufacturing cost of test device increases
Solution Approach 1:
The existing pads are designed to perform multiple functions: they serve as data input/output pads during normal operation and as data strobe pads during DDR testing. This multi-functionality eliminates the need for dedicated data strobe pads, reducing test device manufacturing cost while maintaining DDR test functionality
Solution Approach 2:
The patent combines the functionality of data pads and data strobe pads into a single set of pads. By merging these functions and using signal routing control to switch between modes, the invention reduces the total number of pads required, thereby lowering test device complexity and manufacturing cost
2Reliability
If multiple pads are used for testing, then comprehensive test coverage is achieved, but device complexity increases
Solution Approach 1:
The patent implements dynamic pad functionality where the same physical pads can be dynamically reconfigured for different testing purposes. Through control signals and timing mechanisms, the pads switch between data transfer mode and data strobe mode, maintaining comprehensive test coverage while reducing the static number of required pads
Solution Approach 2:
By designing pads with universal functionality that adapts to different test requirements through control logic, the invention reduces the total pad count while ensuring comprehensive DDR test coverage is achieved through proper signal routing and timing control
Data Source
AI summary
A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.