DDR Memory Controller Timing Calibration Without Asynchronous FIFOs
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Solution Overview
Problem
DDR memory controllers face challenges in adapting to system timing irregularities, leading to increased silicon real estate requirements and latency due to the need for numerous delay elements and asynchronous FIFOs, which affect yield and performance.
Innovation Solution
A DDR memory controller design that utilizes core domain clocking mechanisms and self-configuring logic to perform timing calibration during power-on initialization, eliminating delay elements on dq inputs and using a core clock delay element for dqs, thereby reducing silicon usage and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous FIFOs and numerous delay elements are used to handle timing skew, then timing adaptation capability is improved, but silicon real estate requirements and device complexity increase significantly
Solution Approach 1:
The patent extracts the delay adjustment functionality from multiple individual delay elements and concentrates it into a single programmable delay element located in the Phy portion. This single delay element can adjust the timing of the dqs signal to compensate for system timing skew, eliminating the need for numerous delay elements distributed throughout the data path and significantly reducing silicon real estate requirements while maintaining timing adaptation capability
Solution Approach 2:
The single programmable delay element in the Phy portion serves multiple functions: it compensates for timing skew in the dqs signal, synchronizes data capture timing, and adapts to different system implementations. This multi-functional approach replaces what would traditionally require multiple specialized delay elements, reducing overall device complexity
2Adaptability or versatility
If asynchronous FIFOs are used to transfer data between clock domains, then timing skew is handled, but latency increases
Solution Approach 1:
The patent removes the asynchronous FIFO from the data path and replaces it with a synchronous registration approach. Data is captured directly into core domain registers clocked by core_clk, with timing adjustment achieved through the programmable delay element on dqs in the Phy portion. This eliminates the multi-cycle transfer delay inherent in asynchronous FIFOs while still handling timing skew
Solution Approach 2:
The programmable delay element in the Phy portion performs preliminary timing adjustment on the dqs signal before data capture. By pre-synchronizing the dqs timing to match core_clk requirements, the system eliminates the need for additional latency-inducing synchronization stages that would otherwise be required when using asynchronous FIFOs
3Measurement precision
If delay elements are added to dq inputs for timing calibration, then timing accuracy is improved, but silicon real estate requirements increase
Solution Approach 1:
The patent consolidates all delay adjustment functionality into a single programmable delay element that operates on the dqs signal in the Phy portion. This single element provides sufficient timing calibration for the entire system by adjusting the strobe timing relative to data, eliminating the need for separate delay elements on each dq input line and significantly reducing silicon real estate requirements
Solution Approach 2:
The patent merges the timing calibration function that would traditionally be distributed across multiple delay elements on dq lines into a single centralized programmable delay element on the dqs signal. This consolidation achieves the same timing accuracy while using fraction of the silicon real estate
Data Source
AI summary
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.