DDR4 Input Receiver Noise Suppression During Write Strobe Off
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Solution Overview
Problem
In low power DDR4 dynamic random access memory (DRAM), control signals violating timing definitions can cause noise amplification during a write data strobe signal off period, leading to circuit malfunctions.
Innovation Solution
A noise suppression circuit with resistors and switches connected in series between the input terminals of a differential amplifier is activated during the write data strobe signal off period to prevent noise amplification by forming a voltage dividing circuit, using transistors to control switch states based on data strobe signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the on die terminator (ODT) is maintained to an off state during write data strobe signal off period, then power consumption is reduced, but noise signals are amplified causing circuit malfunction
Solution Approach 1:
The noise suppression circuit is activated in advance during the write data strobe signal off period before the write preamble period begins. This preliminary action ensures that any noise signals present during this period are suppressed before they can be amplified by the differential amplifier, thus preventing circuit malfunction while maintaining low power consumption by keeping ODT off.
Solution Approach 2:
A noise suppression circuit is introduced as an intermediary component between the data strobe signal input and the differential amplifier. This intermediary circuit includes switches and resistors that are activated during the write data strobe signal off period to suppress noise signals, thereby protecting the downstream circuit from noise amplification while allowing the ODT to remain off for power savings.
2Reliability
If the noise suppression circuit is activated during write data strobe signal off period, then noise signals are suppressed, but device complexity increases
Solution Approach 1:
The noise suppression circuit is merged with the existing input receiving circuit structure. The switches and resistors are integrated into the signal path at the differential amplifier input, combining the noise suppression function with the existing data reception functionality rather than adding a completely separate system.
Solution Approach 2:
The noise suppression circuit operates periodically only during the write data strobe signal off period before the write preamble period, rather than continuously. This time-limited operation is controlled by detecting the specific timing window, which reduces the overall activity of the suppression circuit and minimizes its impact on device complexity while maintaining effectiveness during critical periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively suppresses noise signals from causing circuit malfunctions by dividing their voltage, preventing them from reaching harmful levels during data transmission.
Implementation Method 1
provides a noise suppression resistor connected between the input terminal of the input receiving circuit and a ground voltage during a write data strobe signal off period before a write preamble period
Data Source
AI summary
A memory device and a noise suppression method thereof are provided. An input receiving circuit of a memory circuit receives a data strobe differential signal pair. A noise suppression circuit provides a noise suppression resistor connected between an input terminal of the input receiving circuit and a ground voltage during a write data strobe signal off period before a write preamble period.