Inter-Die Data and ECC Links for DDR5 TSV Timing Limits
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Solution Overview
Problem
The increased clock speed in DDR5 memory devices exceeds the tolerances of existing inter-die connectors like through-silicon vias (TSVs), requiring a modified memory device architecture to accommodate the higher burst length, which was not effectively addressed in DDR4 designs.
Innovation Solution
The integration of separate inter-die error correction connectors to handle error correction information separately from data connectors, allowing for faster data transfer and error detection between master and target dies, using error correction circuitry to ensure accurate data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the burst length is increased to sixteen in DDR5, then the data transfer capacity is improved, but the clock speed increases beyond the tolerances of existing inter-die connectors
Solution Approach 1:
The patent divides the transmission of data and error correction information into separate inter-die connectors. Data bits are transmitted through data connectors while error correction bits are transmitted through dedicated error correction connectors, allowing independent optimization of each transmission path and avoiding the need to increase clock speed for the entire system.
Solution Approach 2:
The patent introduces separate error correction connectors as intermediary transmission paths. These dedicated connectors handle error correction information separately from data, acting as a mediator that allows the system to maintain lower clock speeds while still achieving the required data transfer capacity through the sixteen-bit burst length.
2Speed
If the clock speed is increased to accommodate the higher burst length, then the data transfer rate is improved, but the inter-die connectors such as TSVs exceed their operational tolerances
Solution Approach 1:
The patent segments the data transmission function into separate paths: data bits travel through data connectors while error correction bits travel through error correction connectors. This segmentation allows each connector type to be optimized for its specific function without requiring increased clock speeds that would exceed TSV tolerances.
Solution Approach 2:
The patent changes the architectural parameters by introducing separate error correction connectors with dedicated transmission paths. This parameter change allows the system to maintain lower clock speeds within TSV tolerances while still achieving high data transfer rates through the sixteen-bit burst length capability.
3Reliability
If separate error correction connectors are integrated, then error detection reliability is improved, but the device complexity increases
Solution Approach 1:
The patent segments error correction transmission into dedicated connectors, which improves error detection reliability by providing separate, optimized paths for error correction information. While this increases the number of connectors, each connector maintains a simple, dedicated function that reduces the complexity of individual connector design and operation.
Data Source
AI summary
Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.