DDS Phase Accumulator Correction for Multi-Synthesizer Alignment

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Solution Overview

Problem

Existing direct digital synthesizers require precise, time-critical coordination for setting the initial phase values to achieve a predefined phase relation, which is challenging in measurement setups involving multiple synthesizers.

Innovation Solution

A direct digital synthesizer circuit with a phase accumulator that includes a phase correction sub-circuit, allowing for the adaptation of the phase signal fed back to the phase increment sub-circuit based on a phase shift word, enabling a less time-critical setting of the phase relation between synthesizers, and a converter circuit to generate signals of arbitrary shape.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If initial phase values are set simultaneously within a single clock cycle, then a desired phase relation between multiple direct digital synthesizers is achieved, but the operation becomes time-critical and difficult to coordinate

Engineering Contradiction:
Improvephase relation precisionVSAvoidoperation timing complexity
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent segments the phase setting process into two independent parts: (1) frequency tuning word (FTW) setting that determines phase increment, and (2) initial phase setting that determines starting phase. This segmentation allows each parameter to be set independently without requiring precise simultaneous coordination, as the phase relation is established through the combination of these separately controllable parameters rather than through tightly synchronized initialization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-calculating and storing the relationship between frequency tuning words and phase increments in a lookup table or register. This allows the system to establish the desired phase relation through pre-prepared configuration data rather than requiring real-time coordinated adjustment of multiple synthesizers, eliminating the time-critical simultaneous setting requirement

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If precise simultaneous initialization is required, then accurate phase relation is achieved, but the device complexity and coordination requirements increase

Engineering Contradiction:
Improvephase relation accuracyVSAvoidcoordination mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback by using the phase accumulator's natural accumulation behavior to maintain consistent phase relationships. The phase accumulator continuously accumulates the frequency tuning word to generate phase values, and this feedback mechanism ensures that phase relations remain stable and accurate over time without requiring complex external coordination, as the system self-regulates through its inherent accumulation process

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies self-service by designing the phase accumulator to automatically maintain phase relations through its inherent accumulation function. Each synthesizer independently generates its phase sequence by accumulating its own frequency tuning word, and the phase relation between multiple synthesizers is maintained through their respective accumulation rates rather than through complex inter-synthesizer coordination mechanisms

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12608036B2Direct digital synthesizer circuit, measurement system, and method of operating a direct digital synthesizer circuit
Publication Date: 2026.04.21 ROHDE & SCHWARZ GMBH & CO KG
  • US12608036B2 patent drawing
  • US12608036B2 patent drawing
  • US12608036B2 patent drawing

AI summary

A DDS circuit includes a phase accumulator circuit. The phase accumulator circuit includes a clock input being configured to receive a clock signal. The phase accumulator circuit includes a frequency tuning register configured to receive a frequency tuning word (FTW), and a phase shift register configured to receive a phase shift word (PSW). The phase accumulator circuit also includes a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal and/or based on the FTW. The phase accumulator circuit further includes a feedback path configured to feed back the phase signal to the phase increment sub-circuit. The phase accumulator circuit further includes a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word.