Dead Time Optimization Using Synchronous Detection
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Solution Overview
Problem
Existing power loss minimizing dead time (PLMDT) schemes face challenges such as instrumentation errors, local power loss minima, and coherent load transients, which affect the accuracy and reliability of dead time optimization in switching power supplies.
Innovation Solution
The implementation of a mixed signal approach with a signed accumulator for power loss measurement, pseudo-random timing for load transient management, and enhanced comparator offset cancellation to improve resolution and repeatability, allowing for broader dead time testing and reduced interference from coherent load changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sample and hold (S&H) circuit is used with a comparator to store and compare power loss samples, then power loss comparison capability is improved, but input bias and offset current errors increase measurement uncertainty
Solution Approach 1:
The patent uses a copy of the error amplifier output signal to feed the S&H circuit and comparator, rather than directly using the original signal. This copying approach allows the measurement circuit to operate without loading the original control path, reducing measurement errors while maintaining system functionality.
Solution Approach 2:
The patent employs inexpensive, easily replaceable components for the S&H circuit and comparator, accepting that these components will have inherent offsets that can be recalibrated or replaced rather than designing for perfect component specifications. This pragmatic approach reduces overall system cost and complexity.
2Loss of energy
If the dead time is modulated to find minimum power loss, then power loss minimization capability is improved, but the system becomes susceptible to coherent load transients that can overwhelm the measurement signal
Solution Approach 1:
The patent implements periodic modulation of the dead time parameter at a specific frequency, allowing the system to scan through different dead time values systematically. This periodic action enables the extraction of power loss information through synchronous detection while maintaining controlled experimentation conditions.
Solution Approach 2:
The patent introduces an intermediary measurement process that uses the error amplifier output as an indirect indicator of power loss, rather than directly measuring power loss. This intermediary signal can be processed through filtering and synchronous detection to extract meaningful information while rejecting transient interference.
3Productivity
If analog signal processing is used with amplifiers and comparators, then continuous signal processing capability is improved, but offset errors of 1 mv or lower are difficult to achieve economically
Solution Approach 1:
The patent replaces precision analog component design with a digital processing approach, using microprocessor-based synchronous detection and digital filtering to achieve the required measurement precision. This substitution allows standard, inexpensive analog components to be used while achieving high measurement accuracy through software-based error rejection.
Solution Approach 2:
The patent implements feedback through synchronous detection where the modulated dead time control signal is used to gate and average the error amplifier output signal. This feedback mechanism selectively amplifies the component of the error signal that correlates with dead time variations while rejecting uncorrelated noise and offset errors.
4Reliability
If simple averaging is used to eliminate random load transients, then noise reduction is improved, but coherent load transients with frequencies near the PLMDT sample frequency can still overwhelm the desired signal
Solution Approach 1:
The patent uses periodic modulation of the dead time at a known frequency, which creates a corresponding periodic component in the error amplifier output. This allows the use of synchronous detection with a reference signal at the same frequency to selectively extract the dead time-related information while rejecting other periodic disturbances including coherent load transients.
Solution Approach 2:
The patent performs preliminary modulation of the dead time parameter in a controlled manner before attempting to measure power loss effects. This preliminary action establishes a known reference pattern that can be used for synchronous detection, allowing the system to distinguish between intentional dead time variations and external load transient effects.
Data Source
AI summary
Apparatus for minimizing power losses associated with dead time between ON times of two series connected switches of a power converter connected across a supply potential, the apparatus comprising a control arrangement for monitoring a selected parameter associated with power loss during the dead time of the converter; the control arrangement changing the dead time from a first dead time to a second dead time and comparing the selected parameter associated with power loss for the first and second dead times and determining which of the power losses associated with the two dead times is smaller; a dead time implementing stage for implementing the two dead times; and the control arrangement selecting the dead time associated with the smaller power loss and providing a signal to the dead time implementing stage to set the selected dead time, wherein the control arrangement comprises a module sampling a signal related to the selected parameter associated with power loss at selected instants in time corresponding to the first and second dead times; and a processor for controlling timing of the sampling; and further comprising a comparator module for comparing power loss associated with the first and second dead times and for providing a signal indicating which dead time is associated with a smaller power loss and providing said signal to said processor to implement the dead time associated with the smaller power loss; further comprising an error compensating circuit coupled to said sampling module and to said comparator to reduce offset errors, introduced by either or both said sampling module and said comparator module. Also described is an apparatus to prevent trapping at sub-optimal dead times and for compensating for coherent load transients.