Debug Master Command Translator for Non-Invasive SoC Cache Access
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Solution Overview
Problem
Current debugging schemes for system-on-chip integrated circuits are either invasive, requiring halted processing, or non-invasive but limited in performance monitoring and instruction tracing.
Innovation Solution
An integrated circuit with system-on-chip circuitry and programmable logic, featuring a debug master that can be programmed to perform debug operations without halting processor cores, using a command translator to maintain memory coherency and allow coherent access to cache data through system-on-chip interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If invasive debugging schemes are used to access detailed performance monitoring information, then debugging capability is improved, but processor execution is halted
Solution Approach 1:
A debug master is introduced as an intermediary component that interfaces with the memory coherency control unit through a command translator. This mediator enables detailed debugging operations including performance monitoring and cache access without requiring processor halts, as the debug master communicates coherently with the memory system while the processor continues execution.
2Productivity
If non-invasive debugging schemes are used to maintain processor execution, then productivity is improved, but access to performance monitoring information is limited
Solution Approach 1:
The debug master serves as an intermediary that gains access to detailed performance monitoring information through the memory coherency control unit without disrupting processor execution. The command translator enables the debug master to issue coherent commands to access cache data and performance counters, providing comprehensive debugging information while maintaining non-invasive operation.
Solution Approach 2:
The memory coherency control unit is designed to serve multiple functions: it maintains memory coherency for normal processor operations and simultaneously provides debug access pathways for the debug master. This multi-functionality allows the same hardware infrastructure to support both productive processor execution and comprehensive debugging operations.
3Device complexity
If debug access is provided through existing memory interfaces, then device complexity is reduced, but memory coherency cannot be maintained
Solution Approach 1:
A command translator is introduced as an intermediary between the debug master and the memory coherency control unit. This translator converts debug commands into coherent memory operations, enabling the debug master to access cache and memory data while maintaining memory coherency protocols. The command translator handles the complexity of coherent access internally, keeping the overall device architecture relatively simple.
Data Source
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AI summary
An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master.