Decimal Multiply Algorithm Using Two-Cycle Adder

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Solution Overview

Problem

Decimal floating point multiplication with a two-cycle adder limits performance due to requiring twice as many clock cycles, hindering efficient computation in computer systems.

Innovation Solution

An algorithm that computes one partial product per cycle by utilizing a two-cycle adder, where partial products are generated and accumulated efficiently, allowing for pipelined processing of decimal multiplication operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a two-cycle adder is used for decimal floating point multiplication, then the addition operation can be completed with available hardware resources, but the multiplication operation requires twice as many clock cycles, reducing overall system performance

Engineering Contradiction:
Improvemultiplication throughputVSAvoidclock cycles per multiplication
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The multiplication algorithm is segmented into distinct phases: partial product generation in the first cycle and addition to running sum in the second cycle. This segmentation allows the system to efficiently utilize the two-cycle adder while maintaining an average of one partial product computation per cycle through pipelining.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The running sum is pre-initialized to zero before the multiplication loop begins. This preliminary action eliminates the need for initialization during each multiplication operation, reducing overhead and improving overall throughput.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the addition is broken into two separate steps to prevent the decimal adder from limiting performance, then the adder can be utilized effectively, but the multiplication algorithm becomes more complex and requires careful management of partial products

Engineering Contradiction:
Improveadder utilization efficiencyVSAvoidmultiplication algorithm complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The multiplication algorithm maintains continuous useful action by computing one partial product per cycle and immediately adding it to the running sum. This continuous pipeline ensures that the adder is utilized effectively in both cycles without idle periods, while the algorithmic structure manages complexity through systematic iteration.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The running sum serves as a feedback mechanism that accumulates partial products across multiple cycles. This feedback approach allows the algorithm to manage complexity by maintaining a single accumulative state rather than requiring complex intermediate storage and management of multiple partial products simultaneously.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8140607B2Method for providing a decimal multiply algorithm using a double adder
Publication Date: 2012.03.20 RAKUTEN GROUP INC
  • US8140607B2 patent drawing
  • US8140607B2 patent drawing
  • US8140607B2 patent drawing

AI summary

A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a shifter and initialized to zero. The method includes performing for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand and adding the partial product to the running sum. The running sum is output as the result of multiplying the multiplier and the multiplicand. The performing and outputting are implemented by a mechanism that includes one or more two cycle adders connected to the operand registers, multiplicand multiples circuitry connected to the operand registers, and a result digits register connected to the two cycle adders.