Decision Feedback Equalization Circuit for Memory Data Integrity
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Solution Overview
Problem
Integrated circuit memory devices face challenges in achieving large storage capacity and high data transfer throughput due to data distortion caused by channel loss and inter-symbol interference (ISI).
Innovation Solution
The implementation of a decision feedback equalization (DFE) circuit with a timing adjustment circuit that imposes adjustable delays on data signals, allowing for pulse width tuning on the CMOS level. This circuit includes logic gates to expand pulse widths based on logic values and a multiplexer to select the appropriate output based on equalization feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted through the channel, then data transfer throughput is improved, but data distortion occurs due to channel loss and inter-symbol interference
Solution Approach 1:
The patent implements decision feedback equalization where previous data decisions are fed back to compensate for inter-symbol interference in current data reception. The DFE circuit uses past symbol decisions to generate compensation signals that are subtracted from the received signal, thereby eliminating ISI and improving data reliability while maintaining high throughput
Solution Approach 2:
The equalization process performs preliminary compensation for anticipated interference before the actual data decision is made. By calculating expected ISI from previous symbols and removing it in advance, the system prepares a cleaner signal for decision-making, improving both reliability and throughput
2Reliability
If pulse width is expanded to compensate for distortion, then data valid window is optimized, but circuit complexity increases
Solution Approach 1:
The DFE circuit is segmented into distinct functional blocks: delay elements for storing previous symbols, adders for computing ISI compensation, and decision devices for data detection. This modular segmentation allows each component to perform a specific function efficiently, optimizing the data valid window while keeping overall circuit complexity manageable through structured design
Solution Approach 2:
The circuit dynamically adjusts pulse width parameters through the equalization process. By changing the effective pulse width of data signals through constructive interference compensation, the system optimizes the data valid window without requiring physical changes to the circuit structure, thereby maintaining simplicity while improving reliability
Data Source
AI summary
An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.