Deck Offset Mechanism for Multi-Deck Non-Volatile Memory
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Solution Overview
Problem
Multi-deck non-volatile memory systems face challenges with varying raw bit error rates (RBER) across different decks, leading to inconsistent memory access performance due to differences in electrical characteristics, which existing technologies fail to adequately address.
Innovation Solution
Implementing a deck offset technique that allows for the spreading of memory accesses across multiple decks by modifying the incoming deck address using programmable registers or hardwired settings, enabling access to different physical decks for a given logical address, thereby averaging the RBER across decks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory accesses are concentrated on specific decks, then access speed may be improved for those decks, but the raw bit error rate becomes unacceptably high due to varying electrical characteristics across decks
Solution Approach 1:
The patent applies local quality by recognizing that different decks have different electrical characteristics and error rates, and by selectively distributing accesses to different decks based on their individual qualities. The system monitors RBER per deck and dynamically adjusts access patterns to favor decks with lower error rates while still utilizing multiple decks, thereby optimizing reliability based on local deck conditions.
Solution Approach 2:
The patent implements dynamics by making the deck selection process adaptive rather than static. The system continuously monitors raw bit error rates and dynamically adjusts which decks are accessed and how many bits are read from each deck. This dynamic adjustment allows the system to respond to changing conditions and maintain optimal reliability across varying operational states.
2Reliability
If multiple decks are accessed for each memory access request, then the average raw bit error rate is reduced, but the device complexity increases due to additional addressing and control logic
Solution Approach 1:
The patent applies segmentation by dividing the memory access operation into separate handling for different decks. Instead of treating all decks uniformly, the system segments the access logic to independently control reads from Deck 0 and Deck 1, with separate bit counts and error rate monitoring for each deck. This segmentation makes the complex multi-deck operation more manageable and controllable.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the number of bits read from each deck (first_bit_count, second_bit_count) based on monitored error rates. When one deck exhibits higher errors, the system changes the parameters to read fewer bits from that deck and compensate by reading more bits from the other deck, thereby maintaining overall reliability without requiring complete redesign of the access architecture.
3Reliability
If deck offset is implemented to spread accesses across decks, then error rates are averaged and reduced, but the manufacturing precision requirements increase due to programmable register configurations
Solution Approach 1:
The patent applies preliminary action by pre-configuring offset values in registers before normal operation begins. The deck offset mechanism is set up in advance with predetermined offset values that determine how logical addresses map to physical decks. This preliminary configuration simplifies the manufacturing process, as the offset values can be programmed once during initialization rather than requiring precise physical manufacturing adjustments.
Solution Approach 2:
The patent introduces an intermediary layer in the form of programmable registers that mediate between logical addresses and physical deck mappings. These registers act as a flexible interface that can be configured to implement deck offset without requiring precise manufacturing of the underlying memory structure. The intermediary registers absorb the complexity of address translation, allowing the physical memory array to be manufactured with standard precision.
Data Source
Figure 1A~1B
Figure 1C~2
Figure 3
AI summary
Deck offset techniques for multi-deck non-volatile memory can reduce the average raw bit error rate (RBER) for a memory system. Deck offset can enable accessing different physical decks for the same input deck address. In one example in a system (701) with multiple memory components (703-1,703-U), different physical decks are accessed across multiple memory components for the same logical deck address. In one example in a system with one memory component, different physical decks are accessed across multiple partitions of the same memory component.