Memory Architecture Accessing/Allocation TRIZ Cases
- Hybrid Memory Controller Snapshot Mechanism
Sequential write history logging in non-volatile memory reduces snapshot creation time while ensuring data integrity after power interruption.
- BIOS Integrity Checking via Dedicated Security Module
Direct memory access by a security module hashes BIOS code during reset, eliminating CPU bottlenecks and preventing tampering.
- LBAT Acceleration Component Bulk Memory Update
LBAT acceleration component uses DRAM cache to execute single-operation bulk updates, reducing sequential read-write wait times.
- Multimode Storage Device With Selective Underlying Exposure
Selective underlying exposure separates logical and physical addressing, resolving the trade-off between management complexity and storage speed.
- Memory Access Circuit Parallel Read Prefetching
An accessing circuit maps reference addresses to two SRAMs for parallel read and prefetch operations.
- Hierarchical Cache Maintenance via Eviction Data Integration
Embedding maintenance indication data within evicted data unifies cache upkeep with eviction handling, eliminating idle time between separate operations.
- Multi-Meta Die Storage Balancing Open Blocks
A data storage device aligns host and relocation block closures to minimize open blocks across multiple meta dies.
- Temperature-Aware SSD Caching for Random I/O Optimization
A temperature-aware caching system groups pages by access cost to optimize solid state storage writes.
- FeRAM-DRAM Hybrid Memory Segmentation and Transfer Gate Coupling
Segmenting FeRAM and DRAM arrays with transfer gates reduces polarization fatigue and minimizes refresh cycles.
- Distributed Cache System Decoupling Storage and Compute
A distributed cache system decouples storage and compute resources using a curator to manage data striping across memory hosts.
- Adaptive Prefetch Engine Page Boundary Latency
Prefetch engine tracks page boundary termination rates to set aggressive startup profiles, minimizing latency when crossing real page boundaries.
- Secure Boot Code Update via Hardware Memory Locking
Segmented memory regions and hardware locks isolate boot code from malware, ensuring secure firmware updates without compromising system integrity.
- Deck Offset Mechanism for Multi-Deck Non-Volatile Memory
Deck offset mapping distributes reads across multiple decks, reducing average raw bit error rates despite varying electrical characteristics.
- Flash Memory Wear Leveling via Bit Error Rate Estimation
A memory controller estimates bit error rates to select blocks for data storage and wear leveling operations.
- Slab Memory Management for Machine Learning Training
Slab-based memory management reduces overhead by migrating least recently used segments to secondary storage, resolving GPU DRAM capacity limits.
- Fabric Control Circuit Dynamic Source Throttling
Dynamic source throttling reduces head-of-line blocking in processor fabrics by adjusting request injection rates based on ownership response statistics.
- Non-speculative Lock Elision for Hardware Transactional Memory
Hardware transactional memory uses non-speculative access instructions to check lock availability before executing transactions.
- Fill Buffer Management for High Temporal Locality Data
Segmenting memory with fill buffers reduces power consumption by minimizing cache writes while maintaining throughput.
- Hashed Page Table Blocks for Virtual Address Translation
A hashed page table mechanism organizes entries into equal-sized blocks to accelerate virtual address translation.