Dynamic Address Mapping for Multi-Channel Memory Yield
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Solution Overview
Problem
The increasing size and processing capability of data processing systems, such as AI chips, lead to higher memory bandwidth requirements, but conventional single-channel memory systems are inadequate, resulting in low yield and short service life due to channel failures and degradation from high power consumption and temperature, especially in AI applications.
Innovation Solution
Implementing dynamic address mapping in multi-channel interleaving technology, where available channels are determined based on an available channel mode and channel data-granularity to reroute data transmission, ensuring data is transmitted through functional channels only, thereby improving yield and service life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-channel interleaving technology is implemented to increase memory bandwidth, then processing capability is improved, but channel failures and degradation occur more frequently due to high power consumption and temperature
Solution Approach 1:
The patent implements dynamic channel availability detection and mapping adjustment. The system continuously monitors channel status and dynamically remaps memory addresses to available channels when failures or degradation are detected, transforming the static multi-channel interleaving system into a dynamic one that adapts to changing channel conditions, thereby maintaining reliability while preserving bandwidth capabilities
Solution Approach 2:
The patent changes the operational parameters of the memory system by detecting channel degradation through read operations and adjusting the channel mapping configuration. When channels show signs of failure or degradation, the system modifies the interleaving pattern to exclude problematic channels, effectively changing the system's operational parameters to maintain stability under high power consumption conditions
2Volume of moving object
If data processing system size is reduced with advanced manufacturing processes, then integration is improved, but yield decreases rapidly due to manufacturing defects
Solution Approach 1:
The patent performs preliminary channel availability detection and mapping configuration during manufacturing testing. By pre-identifying defective channels and pre-configuring the address mapping to use only functional channels, the system captures defective chips that would otherwise be discarded, thereby improving yield without compromising the reduced chip size design
Solution Approach 2:
The patent enables the memory system to self-diagnose and self-configure by automatically detecting channel failures and remapping addresses without external intervention. This self-service capability allows defective chips to be identified and reconfigured in the field, effectively improving yield by converting previously defective units into functional products
3Device complexity
If conventional static address mapping is used in multi-channel memory, then system simplicity is maintained, but service life is shortened due to inability to adapt to channel failures
Solution Approach 1:
The patent transforms the static address mapping into a dynamic system that automatically detects channel availability and remaps addresses in real-time. This dynamic adaptation allows the system to continue operating with degraded channels or after failures occur, significantly extending service life despite the added complexity of the detection and remapping mechanism
Solution Approach 2:
The patent implements a feedback mechanism where read operations monitor channel status and trigger remapping actions when degradation or failures are detected. This closed-loop feedback system continuously adapts the address mapping to current channel conditions, enabling the system to extend its service life by responding to and compensating for channel failures rather than failing completely
Data Source
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AI summary
Example embodiments of the present disclosure provide a method, an apparatus, a device and a computer-readable storage medium for storage management. The method for storage management includes: obtaining an available channel mode of a plurality of channels in a memory of a data processing system, the available channel mode indicating availabilities of the plurality of channels, and each of the plurality of channels being associated with a set of addresses in the memory; obtaining a channel data-granularity of the plurality of channels, the channel data-granularity indicating a size of a data block that can be carried on each channel; obtaining a target address of data to be transmitted in the memory; and determining a translated address corresponding to the target address based on the available channel mode and the channel data-granularity.