FIFO Wraparound Address Lookup Table for Cache Management
Solution Overview
Problem
Data storage devices face operational bottlenecks due to the high complexity and resource-intensive map management required for tracking large storage capacities, leading to degraded data I/O throughput performance.
Innovation Solution
A data storage device employs a system-on-chip (SOC) with a first-in-first-out (FIFO) wraparound address lookup table and a second-level map to efficiently manage cache data, allowing for high-speed data transfers without the need for extensive local volatile memory, using a processing core to match logical addresses with cache addresses and route commands between on-chip and non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional map management structures are used to track large storage capacities, then complete data tracking is achieved, but processing complexity and resource consumption increase significantly
Solution Approach 1:
The patent divides the storage address space into multiple segments or regions, each managed by separate map structures. Instead of using a single comprehensive map to track all storage addresses, the system creates multiple smaller maps that cover different address ranges. This segmentation reduces the complexity of individual map management while maintaining complete tracking coverage across the entire storage capacity.
2Speed
If extensive local volatile memory is used for cache management, then high-speed data transfer is enabled, but device cost and power consumption increase
Solution Approach 1:
The patent extracts the cache management functionality from the main processing system and implements it using the segmented map structures. By taking out the cache management task from the traditional volatile memory-based approach, the system can manage cached data using the segmented maps in non-volatile memory, thereby reducing the need for extensive local volatile memory while maintaining high-speed data transfer capabilities.
3Measurement precision
If comprehensive map structures are implemented to manage all storage addresses, then complete data location capability is achieved, but processing time and operational bottlenecks increase
Solution Approach 1:
The patent segments the address space and implements multiple specialized map structures that can be searched in parallel or in an optimized sequence. This segmentation allows the system to locate data more quickly by directing the search to specific map segments based on the target address range, rather than searching through a single comprehensive map structure, thereby reducing processing time while maintaining precise data location capability.
Solution Approach 2:
The patent implements preliminary organization of address mappings into segmented map structures that are pre-sorted and indexed. This preliminary action enables the system to quickly narrow down the search space for data location by first consulting the segmented maps to identify the relevant address range, before performing the actual data retrieval, thus reducing the overall processing time.
Data Source
AI summary
A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.