Hashed Page Table Blocks for Virtual Address Translation
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Solution Overview
Problem
Conventional page table mechanisms face challenges in efficiently translating virtual addresses to real addresses, particularly in modern computer systems with large virtual address spaces, leading to excessive memory consumption and slow translation times due to inefficient use of memory and cache storage.
Innovation Solution
A hashed page table mechanism is introduced, organizing page table entries into equal-sized blocks with shared high-order virtual address portions, using a binary tree structure for address translation, and employing a hash function to determine index addresses, allowing for efficient memory usage and fast translation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional page table mechanisms are used to translate virtual addresses to real addresses, then address translation functionality is provided, but memory consumption is excessive and translation time is slow
Solution Approach 1:
The patent segments the page table into multiple levels (e.g., first-level page table, second-level page table, etc.), where each level contains a portion of the address translation information. This hierarchical segmentation reduces the size of each individual page table structure, enabling more efficient memory usage while maintaining complete address translation capability through sequential level traversal.
Solution Approach 2:
The patent introduces a multi-dimensional hierarchical structure for the page table, transitioning from a flat single-level table to a tree-like multi-level structure. This dimensional change allows the system to manage large virtual address spaces by distributing translation entries across multiple levels, reducing memory consumption and improving cache utilization patterns.
2Adaptability or versatility
If page table entries are stored in memory to support large virtual address spaces, then address translation capability is provided, but cache locality is poor leading to slow access times
Solution Approach 1:
The patent divides the page table into hierarchical segments where frequently accessed translation entries can be cached at upper levels. This segmentation enables better cache utilization by storing recent or frequently used page table entries in faster memory layers, reducing the time penalty for address translation while supporting large virtual address spaces.
Solution Approach 2:
The patent employs asymmetric page table structures where different levels of the hierarchy serve different purposes - upper levels store commonly accessed or recently used translations for fast access, while lower levels provide detailed mappings for the complete virtual address space. This asymmetric organization optimizes both cache performance and address space coverage.
3Quantity of substance
If a hashed page table mechanism with blocks of contiguous entries is used, then memory efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple page table entries into contiguous blocks at each hierarchical level, where a single cache line or memory structure can hold multiple related entries. This merging approach improves memory efficiency by reducing overhead and improving cache utilization, while the hierarchical organization keeps the overall structure manageable despite the increased complexity of handling blocks rather than individual entries.
Data Source
AI summary
A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.